PLLC Registers
137
SPRUH82C – April 2013 – Revised September 2016
Copyright © 2013–2016, Texas Instruments Incorporated
Phase-Locked Loop Controller (PLLC)
Table 7-3. PLL Controller 1 (PLLC1) Registers
Address
Acronym
Register Description
Section
01E1 A000h
REVID
PLLC1 Revision Identification Register
01E1 A100h
PLLCTL
PLLC1 Control Register
01E1 A104h
OCSEL
PLLC1 OBSCLK Select Register
01E1 A110h
PLLM
PLLC1 PLL Multiplier Control Register
01E1 A118h
PLLDIV1
PLLC1 Divider 1 Register
01E1 A11Ch
PLLDIV2
PLLC1 Divider 2 Register
01E1 A120h
PLLDIV3
PLLC1 Divider 3 Register
01E1 A124h
OSCDIV
PLLC1 Oscillator Divider 1 Register
01E1 A128h
POSTDIV
PLLC1 PLL Post-Divider Control Register
01E1 A138h
PLLCMD
PLLC1 PLL Controller Command Register
01E1 A13Ch
PLLSTAT
PLLC1 PLL Controller Status Register
01E1 A140h
ALNCTL
PLLC1 Clock Align Control Register
01E1 A144h
DCHANGE
PLLC1 PLLDIV Ratio Change Status Register
01E1 A148h
CKEN
PLLC1 Clock Enable Control Register
01E1 A14Ch
CKSTAT
PLLC1 Clock Status Register
01E1 A150h
SYSTAT
PLLC1 SYSCLK Status Register
01E1 A1F0h
EMUCNT0
PLLC1 Emulation Performance Counter 0 Register
01E1 A1F4h
EMUCNT1
PLLC1 Emulation Performance Counter 1 Register
7.3.1 PLLC0 Revision Identification Register (REVID)
The PLLC0 revision identification register (REVID) is shown in
and described in
Figure 7-2. PLLC0 Revision Identification Register (REVID)
31
0
REV
R-4481 3C00h
LEGEND: R = Read only; -
n
= value after reset
Table 7-4. PLLC0 Revision Identification Register (REVID) Field Descriptions
Bit
Field
Value
Description
31-0
REV
4481 3C00h
Peripheral revision ID for PLLC0.