Texas Instruments AM1808, Technical Reference Manual

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Registers
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1264 SPRUH82C – April 2013 – Revised September 2016
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Multichannel Buffered Serial Port (McBSP)
25.3.14 Read FIFO Control Register (RFIFOCTL)
The Read FIFO control register (RFIFOCTL) is shown in Figure 25-55 and described in Table 25-38 .
NOTE: The RNUMEVT and RNUMDMA values must be set prior to enabling the Read FIFO. If the
Read FIFO is to be enabled, it must be enabled prior to taking the McBSP out of reset.
Figure 25-55. Read FIFO Control Register (RFIFOCTL)
31 17 16
Reserved RENA
R-0 R/W-0
15 8 7 0
RNUMEVT RNUMDMA
R/W-10h R/W-4h
LEGEND: R = Read only; R/W = Rear/Write; - n = value after reset
Table 25-38. Read FIFO Control Register (RFIFOCTL) Field Descriptions
Bit Field Value Description
31-17 Reserved 0 Reserved
16 RENA Read FIFO enable bit.
0 Read FIFO is disabled. The RLVL bit in the Read FIFO status register (RFIFOSTS) is reset to 0
and the pointers are initialized, that is, the Read FIFO is “flushed.”
1 Read FIFO is enabled. If the Read FIFO is to be enabled, it must be enabled prior to taking the
McBSP out of reset.
15-8 RNUMEVT 0-FFh Read word count per DMA event (32-bit). When the Read FIFO contains at least RNUMEVT
words of data, then an REVT (receive DMA event) is generated to the host/DMA controller. This
value must be set prior to enabling the Read FIFO.
0 0 words
1h 1 word
2h 2 words
... ...
40h 64 words
41h-FFh Reserved
7-0 RNUMDMA 0-FFh Read word count per transfer (32-bit words). Upon a receive DMA event from the McBSP, the
Read FIFO reads
RNUMDMA words from the McBSP. This value must be set prior to enabling the
Read FIFO.
0 0 words
1 1 word
2h-FFh Reserved