MPU Registers
108
SPRUH82C – April 2013 – Revised September 2016
Copyright © 2013–2016, Texas Instruments Incorporated
Memory Protection Unit (MPU)
5.3.7 Fixed Range Start Address Register (FXD_MPSAR)
The fixed range start address register (FXD_MPSAR) holds the start address for the fixed range. The
fixed address range manages access to the DDR2/mDDR SDRAM control registers (B000 0000h–
B000 7FFFh). However, these addresses are
not
indicated in FXD_MPSAR and the fixed range end
address register (FXD_MPEAR), which instead read as 0. The FXD_MPSAR is shown in
Figure 5-9. Fixed Range Start Address Register (FXD_MPSAR)
31
0
Reserved
R-0
LEGEND: R = Read only; -
n
= value after reset
5.3.8 Fixed Range End Address Register (FXD_MPEAR)
The fixed range end address register (FXD_MPEAR) holds the end address for the fixed range. The fixed
address range manages access to the DDR2/mDDR SDRAM control registers (B000 0000h–
B000 7FFFh). However, these addresses are
not
indicated in FXD_MPEAR and the fixed range start
address register (FXD_MPSAR), which instead read as 0. The FXD_MPEAR is shown in
.
Figure 5-10. Fixed Range End Address Register (FXD_MPEAR)
31
0
Reserved
R-0
LEGEND: R = Read only; -
n
= value after reset