Texas Instruments AFE5801EVM, User Manual, Page: 6 / 48

Board Configuration
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2.2 I/O and Power Connectors
The positions and functions of the AFE5801EVM connectors are discussed in this section.
• Analog Inputs Ch1~Ch8 (J1~J8): Single-end analog signal is converted to differential signals by
transformer.
• Low Jitter CLK Source Input (J11): This input accepts clocks with low jitter noise, such as HP8644
output. 20~50MHz 50% duty cycle clock with 1~2Vrms amplitude can be used. When J11 is used,
make sure shunts P4, P5, P6 are removed.
• CLK output (J10): The output of either the U1 output or the on-board 40MHz oscillator output
depending on jumper P4
’ s connection.
• External CLK Input (J9): ADC Clock input, such as FPGA outputs. FPGA outputs must be processed
by U1. Otherwise, the ADC of AFE5801 will not achieve satisfactory performance.
• +5V PWR connector(P10): Power supply input
• USB input (P11): USB interface to control the AFE5801.
• LVDS Outputs Ch1~Ch8 (P13): Differential LVDS data outputs.
2.3 Jumpers and Setup
The board has been set to default mode. Detailed description can be found in Figure 4 and Figure 5 .
6 AFE5801 8-Channel Variable Gain Amplifier (VGA) with Octal High-Speed ADC SLOU257A – October 2009 – Revised July 2011
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