Texas Instruments ADS9817EVM-PDK, User Manual, Page: 18 / 29

6.2 Schematics
Figure 6-1 through Figure 6-4 show the various connections to the ADS9817 device. The digital signals connect
to J27, and the analog signals connect to SMA connectors and input filtering. Figure 6-1 also shows the
decoupling for the device.
AIN1M
55
AIN1P
54
AIN2M
2
AIN2P
1
AIN3M
4
AIN3P
3
AIN4M
6
AIN4P
5
AIN5M
10
AIN5P
9
AIN6M
12
AIN6P
11
AIN7M
14
AIN7P
13
AIN8M
17
AIN8P
16
SMPL_CLK
44
SMPL_SYNC
45
CS
25
PWDN
32
RESET
31
D0
34
D1
35
D2
36
D3
37
DCLKIN
43
DCLKOUT
33
FCLKOUT
40
SCLK
26
SDI
27
SDO
28
SPI_EN
24
VBIAS
20
NC
38
NC
39
NC
50
NC
51
ADS9817IRSHT
U1A
AVDD_1V8
21
AVDD_1V8
49
AVDD_5V
15
AVDD_5V
56
DVDD_1V8
22
DVDD_1V8
47
DVDD_1V8
48
IOVDD
30
IOVDD
41
AGND
7
DGND
23
DGND
46
IOGND
29
IOGND
42
Thermal_Pad
57
REFM
8
REFM
18
REFOUT_2V5
19
REFIO
52
REFM
53
ADS9817IRSHT
U1B
10V
1µF
C19
10V
0.1µF
C20
10V
0.1µF
C21
GND GND GND
5V
10V
1µF
C15
10V
0.1µF
C16
GND GND
10V
0.1µF
C23
GND
1V8_VDD
1V8_VDD
10V
0.1µF
C24
10V
0.1µF
C25
GND GND
1V8_IOVDD
GND
NT1
Net-Tie
GND
10V
1µF
C22
GND
AIN1P
AIN1M
AIN2P
AIN2M
AIN3P
AIN3M
AIN4P
AIN4M
AIN5P
AIN5M
AIN6P
AIN6M
AIN7P
AIN7M
AIN8P
AIN8M
VBIAS
REFOUT_2V5
REFIO
TP2
TP1
RESETz
SMPL_CLK
SMPL_SYNC
DCLKOUT
FCLKOUT
D0
D1
D2
D3
SPI_EN
CSz
SCLK
SDI
SDO
PWDNz
DCLKOUT
FCLKOUT
DATA_D0
DATA_D1
DATA_D2
DATA_D3
SPI_EN
SCLK
CSz
SDI
SDO
PWDNz
RESETz
SMPL_CLK
SMPL_SYNC
33
R10
33
R11
33
R12
33
R13
33
R14
33
R15
33
R22
Figure 6-1. ADS9817 Device Connections
Bill of Materials, Schematics, and Layout www.ti.com
18 ADS9817EVM-PDK Evaluation Module SBAU416 – NOVEMBER 2022
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