Texas Instruments ADS8568EVM-PDK, User Manual, Page: 8 / 35

3.4 Static Signals for ADS8568
The ADS8568 has several static digital configuration pins. The logic state of the pin will determine the operation
of the device. For example, the PAR/SER digital pin will determine if the communication is in parallel or serial
mode. These pins are automatically controlled by the PHI digital controller when the GUI is in "hardware mode".
The logic level on these pins can be monitored using test points on J11 or as shown in
Figure 3-2 . Some
of these digital control pins also have resistors that can be used to configure the logic levels when the PHI
controller is not used.
Figure 3-2 shows the static logic configuration. To set a pin to logic high the resistor
connected to DVDD is installed. To set an input to logic low the resistor connected to GND needs to be installed.
It is important to understand that the configuration of these resistors does not matter when the PHI is used as
it will drive the logic level to whatever the GUI setting is. These digital input configuration resistors only matter
when the EVM is disconnect from the PHI and used with a different digital controller.
Figure 3-2 also shows the operation of the reset control line. This reset can be initiated by the PHI controller or
by the push button switch. Note that RESET is an active high signal so the two reset signals are applied to an
OR function so that the device will be reset if either the push button is pressed or the PHI drives the signal active
high.
DVDD
GND
DVDD DVDD
DVDD
DVDD
DVDD
DVDD
GND
GND GND
GND
GND
GND
10.0k
R59
AS
L
E
EP
DNP
10.0k
R64
~
ST
BY
DNP
1000pF
C56
1
2
S1
GND
ASLEEP ~STBY
~HW_SW ~PAR_SER
RANGE_XCLK REFEN_~WR
H
IGH
LO
W
10.0k
R61
N
ORM
10.0k
R62
N
O
R
M
10.0k
R77
SW
DNP
10.0k
R78
SER
DNP
10.0k
R90
~
H
W
10.0k
R91
~
PAR
10.0k
R102
2
Vref
DNP
10.0k
R103
IN
T
10.0k
R105
4
Vref
10.0k
R106
EXT
DNP
10.0k
R110
10.0k
R111
TP10
REFEN_~WR
TP9
~PAR_SER
TP8
~HW_SW
TP11
RANGE_XCLK
4
1
2
SN74AHC1G32DRLR
U9A
RESET
RESET1
TP13
~STBY
TP12
ASLEEP
Figure 3-2. Static Digital Input Configuration
3.5 I2C Bus for Onboard EEPROM
The circuit shown in Figure 3-3 is used with our EVM controler (PHI), for EVM identification. This circuit is not
required by the ADS8568 for operation. The switch (S2) is a write protect and does not need to be changed for
EVM operation.
GND
GND
ID_PWR
EVM_ID_SCL
EVM_ID_SDA
GND
GND
A0
1
A1
2
A2
3
VSS
4
SDA
5
SCL
6
WP
7
VCC
8
U7
BR24G32FVT-3AG E2
2
1
3
S2
EVM_ID_WP
100nF C59
100nF
C60
10.0k
R112
Figure 3-3. EEPROM for EVM ID
Digital Interface www.ti.com
8 ADS8568EVM-PDK Evaluation Module SBAU193E – JUNE 2011 – REVISED MAY 2021
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