background image

Figure 7-4

 shows the ADC decoupling, digital connections, and reference connections.

10u F

C75 

GND 

49. 9

R81 

49. 9

R82 

49. 9

R83 

B VDD

3.6 V

D7

Ze ner 

EVM _ID_SDA

EVM _ID_SCL

EVM _ID_PWR

GND 

S1

10. 0k 

R101

100 nF 

C74 

GND 

EVM _ID_PWR

GND 

R102

EVM _ID_WP 

DB0/SEL_ A 
DB1/SEL_ B 
DB2/SEL_ C 

DB3/DCIN_C
DB4/DCIN_B
DB5/DCIN_A
DB6/SCL K

DB7/HBEN/DCEN 

DB8/SDO _A 
DB9/SDO _B 

DB10/SDO_C

DB11
DB12

DB13/SDI

DB14/REFBUFEN 

DB15

49. 9

R84 

49. 9

R85 

49. 9

R86 

49. 9

R87 

49. 9

R88 

49. 9

R89 

49. 9

R90 

49. 9

R91 

49. 9

R92 

49. 9

R93 

49. 9

R94 

49. 9

R95 

49. 9

R96 

DB0 /SE L_A 

17

DB1 /SE L_B 

16

DB2 /SE L_C 

15

DB3 /DCIN_ C

14

DB4 /DCIN_ B

13

DB5 /DCIN_ A

12

DB6 /SCLK

11

DB7 /HBEN/DCE N 

10

DB8 /SDO_A 

DB9 /SDO_B 

DB1 0/SDO_ C

DB1 1

DB1 2

DB1 3/SDI

DB1 4/REFBUF EN 

DB1 5

64

CONVST_A

23

CONVST_B

22

CONVST_C

21

CH_ A0  

33

CH_ A1  

36

CS/FS 

19

RD

20

STBY

24

BUSY/INT

18

HW/SW 

62

PAR/SER 

61

RANGE/XCLK

27

REFE N/WR

63

REFIO 

51

RESET 

28

WORD/BY TE 

29

CH_ B0  

39

CH_ B1  

42

CH_ C0  

45

CH_ C1  

48

REFC_A

54

REFC_B

56

REFC_C

58

ADS85 55SPM R 

U2A 

GND 

GND 

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51

53

53

55

55

57

57

59

59

10

10

12

12

14

14

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

32

32

34

34

36

36

38

38

40

40

42

42

44

44

46

46

48

48

50

50

52

52

54

54

56

56

58

58

60

60

GND 

MP1  

GND 

MP2  

GND 

MP3  

GND 

MP4  

J2

QT H-030 -01-L-D-A

EVM _ID_SDA
EVM _ID_SCL

EVM _ID_WP 

DB3/DCIN_C
DB4/DCIN_B

DB0/SEL_ A 
DB1/SEL_ B 

DB6/SCL K

DB7/HBEN/DCEN 

DB8/SDO _A 
DB9/SDO _B 

DB10/SDO_C

DB11
DB12

DB13/SDI

DB14/REFBUFEN 

DB15

49. 9

R80 

49. 9

R79 

49. 9

R78 

49. 9

R77 

49. 9

R76 

49. 9

R75 

49. 9

R74 

49. 9

R73 

49. 9

R72 

49. 9

R71 

BUSY/INT

HW/SW 
REFEN/WR

STBY

CS/FS 

~RD 

WORD/BYTE 

PAR/SER 

J5

TSW-103-07-G-D

PAR/SER 

HW/SW 

REFEN/WR

WORD/BYTE 

STBY

~RD 
CS/FS 
BUSY/INT

RESET 

RESET 

RANG E/XCLK

RANG E/XCLK

DB2/SEL_ C 

DB5/DCIN_A

10

11

12

13

14

15
17
19

21

23
25
27
29

31

16
18
20
22
24
26
28
30
32

J3

TSW-116 -07-G-D

CH_A0 

CH_B0 

CH_C0 

CH_A1 

CH_B1 

CH_C1 

AVDD

26

AVDD

34

AVDD

35

AVDD

40

AVDD

41

AVDD

46

AVDD

47

AVDD

50

AVDD

60

BVDD

HVDD

31

AGND

25

AGND

32

AGND

37

AGND

38

AGND

43

AGND

44

AGND

49

AGND

52

AGND

53

AGND

55

AGND

57

AGND

59

BGND

HVSS

30

ADS85 55SPM R 

U2B 

GND 

AVDD

10u F

C71 

GND 

GND 

GND 

10u F

C72 

10u F

C73 

49. 9

R97 

49. 9

R98 

49. 9

R99 

CONVST _A

CONVST _B

CONVST _C

10

11

12

13

14

15
17
19

16
18
20

J4

TSW-110 -07-G-D

CONVST _A
CONVST _B
CONVST _C

GND 

GND 

GND 

1µ F 

C1

1µ F 

C2

1µ F 

C3

1µ F 

C4

GND 

1µ F 

C5

1µ F 

C6

GND 

1µ F 

C7

WORD/BYTE 

CONVST _B

CS/FS 

DB3/DCIN_C
DB4/DCIN_B

DB0/SEL_ A 
DB1/SEL_ B 

DB6/SCL K

DB7/HBEN/DCEN 

DB8/SDO _A 
DB9/SDO _B 

DB10/SDO_C

DB11
DB12

DB13/SDI

DB14/REFBUFEN 

DB15

DB2/SEL_ C 

DB5/DCIN_A

SCLK_ RET URN 

~RD 

BUSY/INT

RESET 

STBY

RANG E/XCLK

PAR/SER 

~RD_RETURN

CONVST _C

CONVST _A

HW/SW 

REFEN/WR

GND 

HVSS

HVDD

1µ F 

C27 

GND 

GND 

1µ F 

C28 

B VDD

GND 

49. 9

R35 

SCLK_ RET URN 

EVM _ID_PWR

49. 9

R46 

~RD_RETURN

VIN 

TEMP

GND 

TRIM/NR 

VOUT

REF502 5AIDG KR 

U6A 

GND 

0.2 2

R48 

EXT  

10u F

C38 

GND 

AVDD

1µ F 

C37 

TP 8 

VREF

R47 

INT 

1

 

2

 

3

 

JP06

100 nF 

C39 

GND 

470 nF 
25V 

C40 

GND 

B VDD

B VDD

100 k

R55 

100 k

R56 

100 k

R57 

100 k

R50 

100 k

R49 

TP 1 

5.5 V

DNP 

A0

A1

A2

VSS 

SDA 

SCL 

WP

VCC 

U3

BR24G32 FVT-3AGE2

Figure 7-4. ADC, Reference, and Digital I/O Schematic

www.ti.com

Bill of Materials, Layout, and Schematics

SLAU298A – NOVEMBER 2009 – REVISED MAY 2021

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ADS8555EVM-PDK Evaluation Module

25

Copyright © 2021 Texas Instruments Incorporated

Summary of Contents for ADS8555EVM-PDK

Page 1: ... configuration is achieved through simple static digital input pins hardware mode or through communications to the SPI interface control register configuration in software mode This user s guide covers the circuit description schematic diagram and bill of materials for the ADS8555 circuit board This EVM hardware and software can also be used to support the ADS8556 ADS8557 and ADS8558 devices from ...

Page 2: ...g the GUI 12 6 2 Jumper Settings for the ADS8555EVM 13 6 3 Modifying Hardware and Using Software to Evaluate Other Devices in the Family 14 6 4 EVM GUI Global Settings for ADC Control and Registers 15 6 5 Time Domain Display 16 6 6 Frequency Domain Display 17 6 7 Histogram Display 18 7 Bill of Materials Layout and Schematics 19 7 1 Bill of Materials 19 7 2 Board Layout 22 7 3 Schematics 23 8 Revis...

Page 3: ...s Signal Source Included in kit ADS8555EVM PHI Board xx xxx x x x x xx xx xx xx xx ADS8555 GUI Signal Source 15V 15V GND Figure 1 1 System Connection for Evaluation 1 2 ADS8555EVM Features Six input channels connected to external single ended signals that are source applied to subminiature version A SMA connectors or headers Serial and parallel interface connects to the PHI controller via a 60 pin...

Page 4: ...N_C 14 DB4 DCIN_B 13 DB5 DCIN_A 12 DB6 SCLK 11 DB7 HBEN DCEN 10 DB8 SDO_A 7 DB9 SDO_B 6 DB10 SDO_C 5 DB11 4 DB12 3 DB13 SDI 2 DB14 REFBUFEN 1 DB15 64 CONVST_A 23 CONVST_B 22 CONVS T_C 21 CH_A0 33 CH_A1 36 CS FS 19 RD 20 STBY 24 BUSY INT 18 HW SW 62 PAR SER 61 RANGE XCLK 27 REFEN WR 63 REFIO 51 RESET 28 WORD B YTE 29 CH_B0 39 CH_B1 42 CH_C0 45 CH_C1 48 REFC_A 54 REFC_B 56 REFC_C 58 ADS8555SPMR U2A ...

Page 5: ...an be used to completely bypass the amplifier This diagram only shows one channel but this circuit is repeated six times For other channels see Figure 7 2 GND HVDD HVSS GND 1 00k R01 TP10 A0in 0 R03 1 00k R02 DNP GND 100pF C02 DNP 1 2 3 JP00 TP9 A0 GND GND 100nF C03 100nF C04 GND CH_A0 1 2 3 4 5 OPA209AIDBVR U00 24 9 R04 1000pF C01 AMP BYPS 1 2 3 4 5 J00 220pF C05 Figure 2 2 Amplifier Drive Circui...

Page 6: ...PI The ADS8555 ADC uses SPI serial communication in mode 1 CPOL 0 and CPHA 1 Because the serial clock SCLK frequency can be as fast as 36 MHz the ADS8555EVM offers 47 Ω resistors between the controller and device to aid with signal integrity Typically in high speed SPI communication fast signal edges can cause overshoot these 47 Ω resistors slow down the signal edges in order to minimize signal ov...

Page 7: ...2 GND MP3 GND MP4 J2 QTH 030 01 L D A EVM_ID_SDA EVM_ID_SCL EVM_ID_WP DB3 DCIN_C DB4 DCIN_B DB0 SEL_A DB1 SEL_B DB6 SCLK DB7 HBEN DCEN DB8 SDO_A DB9 SDO_B DB10 SDO_C DB11 DB12 DB13 SDI DB14 REFBUFEN DB15 1 2 3 4 5 6 J5 TSW 103 07 G D PAR SER HW SW REFEN WR WORD BYTE STBY RD CS FS BUSY INT RESET RANGE XCLK DB2 SEL_C DB5 DCIN_A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 17 19 21 23 25 27 29 31 16 18 20 22 ...

Page 8: ...eet Figure 4 1 also shows how each supply has a light emitting diode LED monitor for quick verification that power is applied Green 1 2 D4 APT2012LZGCK HVSS HVDD GND GND HVSS HVDD AVDD Green 1 2 D5 APT2012LZGCK GND 6 65k R20 AVDD Green 1 2 D3 APT2012LZGCK BVDD Green 1 2 D6 APT2012LZGCK GND 6 65k R30 BVDD 10 0k R18 10 0k R19 GND D1 SMAJ15A GND D2 SMAJ15A GND 10µF C20 10µF C26 15V 15V 1 2 3 J1 Figur...

Page 9: ...NSE 3 6P4V2 4 6P4V1 5 3P2V 6 GND 7 1P6V 8 0P8V 9 0P4V 10 0P2V 11 0P1V 12 EN 13 NR 14 IN 15 IN 16 NC 17 NC 18 NC 19 OUT 20 PAD 21 TPS7A4700RGWR U1 GND GND GND GND 0 R27 0 R26 DNP HVDD 0 R40 DNP 0 R36 25V 22uF C29 100k R29 1µF 25V C36 25V 10uF C30 0 R45 DNP 0 R39 0 R38 DNP 0 R37 DNP 0 R28 0 R25 OUT 1 NC 2 SENSE 3 6P4V2 4 6P4V1 5 3P2V 6 GND 7 1P6V 8 0P8V 9 0P4V 10 0P2V 11 0P1V 12 EN 13 NR 14 IN 15 IN...

Page 10: ... in Figure 5 1 to complete the installation Figure 5 1 ADS8555 Software Installation Prompts As a part of the ADS8555EVM GUI installation a prompt with a Device Driver Installation as shown in Figure 5 2 appears on the screen Click Next to proceed Figure 5 2 Device Driver Installation Wizard Prompts Installing the ADS8555EVM Software www ti com 10 ADS8555EVM PDK Evaluation Module SLAU298A NOVEMBER...

Page 11: ...me Engine Installation Verify that C Program Files x86 Texas Instruments ADS8555EVM is as shown in Figure 5 4 after these installations Figure 5 4 ADS8555EVM GUI Folder Post Installation www ti com Installing the ADS8555EVM Software SLAU298A NOVEMBER 2009 REVISED MAY 2021 Submit Document Feedback ADS8555EVM PDK Evaluation Module 11 Copyright 2021 Texas Instruments Incorporated ...

Page 12: ...s takes a few seconds afterwards the AVDD and DVDD power supplies turn on 5 Connect the external 15 V power supplies and GND to J1 This connection generates the AVDD HVDD and HVSS supplies HVDD 12 V HVSS 12 V and AVDD 5 V 6 Connect the signal generator The default input range is 10 V or 10 Vpk A common input signal applied is a sinusoidal 1 kHz 9 9 Vpk signal with a 0 V offset This signal is adjus...

Page 13: ...uts signals or if the amplifier is bypassed Choosing AMP connects the amplifier between each SMA connector JP00 JP05 and the ADC input The default amplifier configuration is noninverting gain 1 V V The amplifier gain configuration can be adjusted by soldering and desoldering different resistors Choosing the bypass configuration BYPS connects the SMA connectors directly to the ADC input JP06 INT EX...

Page 14: ...talled When this procedure is successfully completed the status bar at the top of the software updates according to the device installed on the hardware Table 6 2 Compatible Devices DEVICE RESOLUTION PARALLEL DATA RATE SERIAL DATA RATE OTHER FEATURE ADS8555 16 630 450 Does not have partial power down mode ADS8556 16 630 450 ADS8557 14 670 470 ADS8558 12 730 500 Use tweezers to change position of s...

Page 15: ...ich page is selected Also if Hardware mode is used the hardware input select pins on the device are set according the controls on the left hand side For example when in hardware mode if the Parallel Interface is selected than the PAR SER pin on the device is driven low by the PHI to select parallel interface mode Select Software_ mode to access the Register Map Config_ Select different Pages_ here...

Page 16: ...ted in Figure 6 6 by using the Capture button The sample indices are on the x axis and there are two y axes showing the corresponding output codes as well as the equivalent analog voltages based on the specified reference voltage Switching pages to any of the analysis tools described in the subsequent sections causes calculations to be performed on the same set of data Figure 6 6 Time Domain Displ...

Page 17: ...igate the effects of noncoherent sampling this discussion is beyond the scope of this document The 7 term Blackman Harris window is the default option and has sufficient dynamic range to resolve the frequency components of up to a 24 bit ADC The None option corresponds to not using a window or using a rectangular window and is not recommended Figure 6 7 Frequency Domain Display www ti com ADS8555E...

Page 18: ...he input drive circuits the reference drive circuit the ADC power supply and the ADC itself is reflected in the standard deviation of the ADC output code histogram that is obtained by performing multiple conversions of a DC input applied to a given channel As shown in Figure 6 8 the histogram corresponding to a DC input is displayed on clicking the Capture button Figure 6 8 Histogram Display ADS85...

Page 19: ... 10 µF 50 V 10 X7R AEC Q200 Grade 1 1206 CGA5L1X7R1H106K160AC TDK C39 C74 2 0 1uF CAP CERM 0 1 uF 50 V 10 X7R 0603 C0603C104K5RACTU Kemet C40 1 0 47uF CAP CERM 0 47 uF 25 V 10 X7R 0603 GRM188R71E474KA12D MuRata D1 D2 2 15V Diode TVS Uni 15 V 24 4 Vc 400 W 16 4 A SMA SMAJ15A Littelfuse D3 D6 4 Green LED Green SMD APT2012LZGCK Kingbright D7 1 3 6V Diode Zener 3 6 V 500 mW SOD 123 MMSZ4685T1G ON Semi...

Page 20: ...V Panasonic R49 R50 R55 R56 R57 5 100k RES 100 k 1 0 0625 W 0402 RC0402FR 07100KL Yageo America S1 1 Switch Slide SPDT 100mA SMT CAS 120TA Copal Electronics SH JP00 SH JP06 7 1x2 Shunt 100mil Flash Gold Black SPC02SYAN Sullins Connector Solutions TP2 TP23 22 Test Point Miniature Black TH 5001 Keystone U00 U05 6 2 2 nV rtHz 18 MHz Precision RRO Operational Amplifier 4 5 to 36 V 40 to 125 degC 5 pin...

Page 21: ... 0 1 00k RES 1 00 k 0 1 0 1 W 0603 RT0603BRB071KL Yageo America R9 R15 R17 R26 R37 R38 R40 R45 0 0 RES 0 5 0 063 W 0402 RC0402JR 070RL Yageo America TP1 0 Test Point Miniature Black TH 5001 Keystone www ti com Bill of Materials Layout and Schematics SLAU298A NOVEMBER 2009 REVISED MAY 2021 Submit Document Feedback ADS8555EVM PDK Evaluation Module 21 Copyright 2021 Texas Instruments Incorporated ...

Page 22: ...yout for the ADS8555EVM Figure 7 1 Board Layout Bill of Materials Layout and Schematics www ti com 22 ADS8555EVM PDK Evaluation Module SLAU298A NOVEMBER 2009 REVISED MAY 2021 Submit Document Feedback Copyright 2021 Texas Instruments Incorporated ...

Page 23: ... P GN D 100p F C42 DN P 1 2 3 JP0 4 TP13 C0 GN D GN D 100n F C43 100n F C44 GN D GN D HV DD HV S S GN D 1 00k R51 TP16 C1in 0 R53 1 00k R52 DN P GN D 100p F C52 DN P 1 2 3 JP0 5 TP15 C1 GN D GN D 100n F C53 100n F C54 GN D CH_A0 CH_A1 CH_B0 CH_B1 CH_C 0 CH_C 1 1 2 3 4 5 OPA209 AIDBVR U00 1 2 3 4 5 OPA209 AIDBVR U01 1 2 3 4 5 OPA209 AIDBVR U02 1 2 3 4 5 OPA209 AIDBVR U03 1 2 3 4 5 OPA209 AIDBVR U04...

Page 24: ... 15V GN D 10 0 k R7 50V 10nF C17 50V 10nF C19 GN D 25V 10uF C16 GN D TP3 15V 25V 10uF C18 GN D 0 R5 0 R4 GN D GN D GN D GN D 0 R27 0 R26 DN P HVD D HVSS 15V 15 V 1 2 3 J1 0 R40 DN P 0 R36 25V 22uF C29 100k R29 1µF 25V C36 25V 10uF C30 0 R45 DN P 0 R39 0 R38 DN P 0 R37 DN P 0 R28 0 R25 OU T 1 NC 2 SEN SE 3 6P4V2 4 6P4V1 5 3P2V 6 GN D 7 1P6V 8 0P8V 9 0P4V 10 0P2V 11 0P1V 12 EN 13 NR 14 IN 15 IN 16 N...

Page 25: ...49 9 R74 49 9 R73 49 9 R72 49 9 R71 BUSY INT HW SW REFEN WR STBY CS FS RD WORD BYTE PAR SER 1 2 3 4 5 6 J5 TSW 103 07 G D PAR SER HW SW REFEN WR WORD BYTE STBY RD CS FS BUSY INT RESET RESET RAN G E XCLK RAN G E XCLK DB2 SEL_ C DB5 DCIN_A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 17 19 21 23 25 27 29 31 16 18 20 22 24 26 28 30 32 J3 TSW 116 07 G D CH_A0 CH_B0 CH_C0 CH_A1 CH_B1 CH_C1 AVDD 26 AVDD 34 AVDD ...

Page 26: ...es from Revision November 2009 to Revision A May 2021 Page Changed entire document because of substantial changes in EVM hardware and software 1 Revision History www ti com 26 ADS8555EVM PDK Evaluation Module SLAU298A NOVEMBER 2009 REVISED MAY 2021 Submit Document Feedback Copyright 2021 Texas Instruments Incorporated ...

Page 27: ...other than TI b the nonconformity resulted from User s design specifications or instructions for such EVMs or improper system design or c User has not paid on time Testing and other quality control techniques are used to the extent TI deems necessary TI does not test all parameters of each EVM User s claims against TI under this Section 2 are void if User fails to notify TI of any apparent defects...

Page 28: ... These limits are designed to provide reasonable protection against harmful interference in a residential installation This equipment generates uses and can radiate radio frequency energy and if not installed and used in accordance with the instructions may cause harmful interference to radio communications However there is no guarantee that interference will not occur in a particular installation...

Page 29: ...y for convenience and should be verified by User 1 Use EVMs in a shielded room or any other test facility as defined in the notification 173 issued by Ministry of Internal Affairs and Communications on March 28 2006 based on Sub section 1 1 of Article 6 of the Ministry s Rule for Enforcement of Radio Law of Japan 2 Use EVMs only after User obtains the license of Test Radio Station as provided in R...

Page 30: ... any interfaces electronic and or mechanical between the EVM and any human body are designed with suitable isolation and means to safely limit accessible leakage currents to minimize the risk of electrical shock hazard User assumes all responsibility and liability for any improper or unsafe handling or use of the EVM by User or its employees affiliates contractors or designees 4 4 User assumes all...

Page 31: ...OR DAMAGES ARE CLAIMED THE EXISTENCE OF MORE THAN ONE CLAIM SHALL NOT ENLARGE OR EXTEND THIS LIMIT 9 Return Policy Except as otherwise provided TI does not offer any refunds returns or exchanges Furthermore no return of EVM s will be accepted if the package has been opened and no return of the EVM s will be accepted if they are damaged or otherwise not in a resalable condition If User feels it has...

Page 32: ...s are subject to change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and display of these resources is prohibited No license is granted to any other TI intellectual property right or to any third party intellectual property right TI disclaims responsibility for and you wi...

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