A
B
C
D
D
C
B
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Revision History
REV
ECN Number
Approved
DOCUMENT CONTROL #:
1
3
BlockDiagram.sch
B
DATE:
29-Jul-2004
ADS8401/ADS8405/ADS8411EVM
6446988
+IN
EXT_REF
B_C
S
B_R
D
B_C
O
N
VST
B_BYTE
B_R
ESET
BU
SY
DB
[1
5
...0
]
Analog-to-Digital Converter
Parallel Control
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
P2
Analog Input
1
2
3
4
5
6
7
8
9
10
11 12
13 14
15 16
17 18
19 20
P1
+VA
-VA
B_DB[15...0]
DB
[1
5
...0
]
CS
RD
C
O
N
VST
BYTE
R
ESET
B_BU
SY
BU
SY
B_C
S
B_R
D
B_C
O
N
VST
B_BYTE
B_R
ESET
+AVCC
+VA
-VA
+BVDD
A0
A1
A2
DC_
CS
Power & Digital Buffer
J2
B_DB[15...0]
DB[15..0]
B_DB0
B_DB1
B_DB2
B_DB3
B_DB4
B_DB5
B_DB6
B_DB7
B_DB8
B_DB9
B_DB10
B_DB11
B_DB12
B_DB13
B_DB14
B_DB15
+AVCC
+BVDD
Lijoy Philipose
Lijoy Philipose
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
P3
CS
RD
CONVST
BYTE
RESET
B_BUSY
A0
A1
A2
1
2
3
4
5
6
7
8
9
10
J1
+VA
-VA
+BVDD
AGND
+AVCC
DGND
TP10
TP11
TP12
TP14
W4
ADC Control
1
2
3
4
5
6
7
8
9
11
10
12
J3
BUSY
DC_CS
