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Digital Interface
3.1
Using TAG Features via W8, W9, and W10
3.2
Additional Digital Control and Monitoring
4
Power Supplies
Digital Interface
The ADS78/8509 EVM is designed for easy interfacing to multiple control platforms. Jumper options are
provided on the EVM to allow direct control over the serial clock source as well as the data output and
TAG features.
The active low CS0 pin is connected to J2 pin 1. This pin can be controlled through GPIO functions on the
5–6K Interface Board or the HPA449. For standalone operation, a shunt jumper can be placed between
J2T pins 1 and 2 to tie CS to ground.
The DATA output from the EVM is applied to W9. When the supplied shunt is on pins 1-2 (default state),
the DATA output is fed to J2B (bottom side) pin 11. This is required when operating in the internal data
clock mode, where the ADC supplies an SPI master clock to the host processor. Data is input to the SIMO
pin of the host in this case. W13 is provided as a means to return the ADC generated SPI clock to DSP
host processors using the 5-6K Interface Board.
W8 controls the TAG function of the ADC. With the supplied shunt in position 1-2 (default state), TAG is
grounded and the EVM is to be considered as either the only converter in the system, or the LAST
converter in the data chain (see
for additional details). When the shunt on W8 is moved to
position 2–3, data input to the TAG pin is fed from J2T (top side) pin 13. W8 and W9 must be in position
1-2 for the last converter in the chain and position 2–3 for all other devices when using the TAG feature.
The TAG feature also requires the use of an external data clock. W10 sets the EXT/INT pin high (external
clock) when the pins are open (no shunt installed). The external data clock can be applied to J2 pin 3 (top
or bottom side).
As mentioned previously, W10 controls the selection of the internal or external data clock. When W10 is
closed (default) the ADC generates a low dwelling burst mode clock that allows the user to read valid data
on either the rising or falling edge. Removing the shunt from W10 requires an external data clock applied
to J2 pin 3 (top or bottom side) to produce a data output stream. W11 controls the data format; when
closed (default) the DATA output pin provides a Binary Twos Complement data stream. Opening W11
provides a straight binary output of the conversion results. W14 controls the device power down function.
Opening W14 applies a logic high to the PWRD pin, shutting down the ADC. W14 can be wired to GPIO
output J2 pin 19 for use with the HPA449 board.
Test points TP4 and TP6 provide access to the SYNC and BUSY signals respectively. These can be
monitored by referencing an oscilloscope to TP5, digital ground (labeled DGND). The applied digital
voltage can be monitored at TP3. Analog signals and the applied VANA voltage can be monitored at TP2
(+5V) referenced to TP1 (AGND).
The ADS78/8509 EVM board re5V DC for both the analog and digital sections of the ADC. Power
to the ADC is sourced from J3 pin 3 and pin 10 (+5VA and +5VD - see table below).
Note:
VDIG must be less than or equal to VANA.
The following table shows the pin out of J3:
Table 3. Pinout of J3
Signal
Pin Number
Signal
+VA
1
2
-VA
ADS78/8509 EVM User's Guide
SLAU140 – November 2004
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