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SBAU342A – February 2020 – Revised June 2020

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ADS7066EVM-PDK Evaluation Module

User's Guide

SBAU342A – February 2020 – Revised June 2020

ADS7066EVM-PDK Evaluation Module

The ADS7066 Evaluation Module (EVM) Performance Demonstration Kit (PDK) allows users to evaluate
the functionality of Texas Instruments' ADS7066 16-bit, eight-channel programmable successive
approximation register (SAR) analog-to-digital converter (ADC). The ADS7066 device showcases eight
inputs, each configurable to an analog input, digital output, or digital input. The device supports an internal
reference as well as operation with an external reference. This user’s guide describes both the hardware
platform showcasing the ADS7066 device and the graphical user interface (GUI) software used to
configure the various modes of operation of this device. It includes complete circuit descriptions,
schematic diagrams, and a bill of materials. The EVM-PDK eases the evaluation of the ADS7066 device
with hardware, software, and computer connectivity through the universal serial bus (USB) interface.

Figure 1. ADS7066EVM-PDK Assembled

The following related documents are available through the Texas Instruments website at www.ti.com.

Table 1. Related Documentation

Device

Literature Number

ADS7066

SBAS928

REF6025

SBOS708B

OPA325

SBOS637D

TPS78001

SBVS083E

Summary of Contents for ADS7066EVM-PDK

Page 1: ...tal input The device supports an internal reference as well as operation with an external reference This user s guide describes both the hardware platform showcasing the ADS7066 device and the graphic...

Page 2: ...anding Page 8 8 ADS7066 Device Configuration Tab Displaying Mode Configuration 9 9 Digital Input or Output Configurations 10 10 Averaging Page 11 11 CRC Function Polynomial 11 12 ADS7066 Data Capture...

Page 3: ...evaluate the ADS7066 device The PAMBoard is controlled by commands received from the ADS7066 GUI and returns data to the GUI for display and analysis If the PAMBoard is not used the EVM plug in module...

Page 4: ...ts Incorporated ADS7066EVM PDK Evaluation Module 2 ADS7066EVM Overview This section describes various onboard components that are used to interface the analog input general purpose inputs outputs GPIO...

Page 5: ...e ended analog input or GPIO for channel 5 of the ADC J5 11 Single ended analog input or GPIO for channel 6 of the ADC J5 12 LED GPO for channel 7 of the ADC J5 3 and J5 4 J5 9 and J5 10 EVM ground 2...

Page 6: ...need to be installed properly To install the EVM to the PAMboard stack the ADS7066EVM PDK board on the PAMBoard Make sure the 20 pin connector J1 J3 on the ADS7066 is mapped to left connector on the...

Page 7: ...ctively 2 On the ADS7066EVM PDK landing page the software is available through a web based GUI Connecting to the GUI may require login to a user account for access 3 First time users may be prompted t...

Page 8: ...device The left corner highlighted by the green rectangle shows the tabs to navigate through the GUI home function configurations data capture and register map When the ADS7066 is stacked on the PAMBo...

Page 9: ...ollowing sampling modes Manual Mode Allows the external host processor to directly request and control when data is sampled The host provides SPI frames to control conversions and the captured data ar...

Page 10: ...o channel 7 to visually display a high or low digital output state To configure for a digital pin change the Pin Config drop down and select Digital A second drop down option will appear in line with...

Page 11: ...e 10 shows the oversampling ratio can be selected through the drop down option The oversampling ratio applies to all analog input channels enabled Figure 10 Averaging Page 3 3 2 4 Cyclic Redundancy Ch...

Page 12: ...displays the sampling mode configuration used to capture the data There is also a checkmark option to repeatedly capture the sample size selected This tab features two pages to display both the analog...

Page 13: ...s for the following Number of samples per the enabled analog input channels A drop down option for increasing the oversampling rate A drop down option to change the SCLK frequency A drop down option f...

Page 14: ...samples can be increased in the Samples Channel drop down menu The data can also be displayed in the volt equivalent of sample captured instead of the code value based in the AVDD When in manual mode...

Page 15: ...lay data if the analog input is AC The FFT tab displays a table with the fundamental frequency of the input followed by the noise floor level SNR SFDR THD and SINAD The effective number of bits ENOB a...

Page 16: ...mentation Feedback Copyright 2020 Texas Instruments Incorporated ADS7066EVM PDK Evaluation Module 3 3 3 1 3 Histogram Graph Display The conversion results can also be shown as a histogram through the...

Page 17: ...S7066EVM PDK Evaluation Module 3 3 4 Digital Input Page The digital input page displays the enabled digital input channels as configured in Figure 9 As an example channel 6 was configured as a digital...

Page 18: ...are broken down into the configurable bits it controls When making changes in the Field View the bit being changed is highlighted in yellow in the register map The register settings can also be saved...

Page 19: ...nput signal requires additional conditioning before the ADC input the ADS7066EVM has an onboard signal conditioning path on channel 0 The input signal header J5 is connected to the amplifier input OPA...

Page 20: ...T C150CKT Lite On J1 J3 2 Receptacle 2 54 mm 10 2 Tin TH SSQ 110 03 T D Samtec J5 1 Header 100 mil 6 2 Tin TH PEC06DAAN Sullins Connector Solutions J6 1 Header 100 mil 2x1 Tin TH SSQ 110 03 T D Samtec...

Page 21: ...entation Feedback Copyright 2020 Texas Instruments Incorporated ADS7066EVM PDK Evaluation Module 5 2 PCB Layout Figure 20 through Figure 22 illustrate the EVM PCB layouts Figure 20 ADS7066 EVM PCB Top...

Page 22: ...S_WS 27 Analog_In I2S_SCLK 28 Analog_Out I2S_SDout 29 Analog_Out I2S_SDin 30 J1 SSQ 110 03 T D GPIO 31 GPIO 32 GPIO 33 GPIO 34 Timer_Cap GPIO 35 Timer_Cap GPIO 36 PWM GPIO 37 PWM GPIO 38 PWM GPIO 39 P...

Page 23: ...ack Copyright 2020 Texas Instruments Incorporated Revision History Revision History NOTE Page numbers for previous revisions may differ from page numbers in the current version Changes from Original F...

Page 24: ...ther than TI b the nonconformity resulted from User s design specifications or instructions for such EVMs or improper system design or c User has not paid on time Testing and other quality control tec...

Page 25: ...These limits are designed to provide reasonable protection against harmful interference in a residential installation This equipment generates uses and can radiate radio frequency energy and if not in...

Page 26: ...instructions set forth by Radio Law of Japan which includes but is not limited to the instructions below with respect to EVMs which for the avoidance of doubt are stated strictly for convenience and s...

Page 27: ...any interfaces electronic and or mechanical between the EVM and any human body are designed with suitable isolation and means to safely limit accessible leakage currents to minimize the risk of electr...

Page 28: ...R DAMAGES ARE CLAIMED THE EXISTENCE OF MORE THAN ONE CLAIM SHALL NOT ENLARGE OR EXTEND THIS LIMIT 9 Return Policy Except as otherwise provided TI does not offer any refunds returns or exchanges Furthe...

Page 29: ...e resources are subject to change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reprod...

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