Texas Instruments ADS58J64 EVM User Manual Download Page 3

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Overview

3

SBAU284 – January 2017

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Copyright © 2017, Texas Instruments Incorporated

ADS58J64 EVM

HP is a registered trademark of Hewlett Packard.
Windows is a registered trademark of Microsoft.
Rohde & Schwarz is a registered trademark of Rohde & Schwarz.

1

Overview

This evaluation board includes the following important features:

Transformer-coupled signal input network, allows a single-ended signal source to the EVM.

LMK04828, a system clock generator, generates the FPGA reference clock for the high-speed serial
interface.

Default transformer-coupled clock input network, tests the receiver performance with a very low-noise
clock.

High-speed serial data output over a standard FMC connector.

Device registers programming through a USB connector and FTDI USB-to-SPI bus translator.

The ADS58J64EVM device is designed to work seamlessly with the TSW14J56EVM device, the
JESD204B data-capture card from TI, and the High-Speed Data Converter Pro (HSDCPro) software tool.
The ADS58J64EVM device is also compatible with many of the development kits from leading FPGA
vendors that contain an FMC connector.

1.1

Required Hardware

The EVM evaluation kit includes the following equipment:

ADS58J64EVM Evaluation Board (EVM)

Mini-USB cable

The EVM evaluation kit

does not

include the following list of equipment, but these items are required for

evaluation of this product, to achieve the best performance.

5-V DC power supply

TSW14J56EVM data capture board, 5-V power supply, and Mini-USB cable

Computer running Windows

®

8, Windows 7, or Windows XP operating system

Two low-noise signal generators

Recommendations: RF generator, > 17 dBm, < –40 dBc harmonics, < 500 fs jitter 20 k – 20 MHz,
and 10 MHz to 2 GHz frequency range

Examples: TSW2170EVM, HP

®

HP8644B, and Rohde & Schwarz

®

SMA100A

Bandpass filter for analog input (between 50 MHz to 500 MHz).

Recommendations: bandpass filter,

60 dB harmonic attenuation,

5% bandwidth, > 18 dBm

power, and < 5 dB insertion loss

Examples: Trilithic 5VH-series Tunable BPF, K&L BT-series Tunable BPF, TTE KC6, or KC7-series
Fixed BPF

Bandpass filter for clock input (various frequencies)

Recommendations: bandpass filter,

60 dB harmonic attenuation,

5% bandwidth, > 18 dBm

power, <5 dB insertion loss

Examples: Trilithic 5VH-series Tunable BPF, K&L BT-series Tunable BPF, TTE KC6 or KC7-series
Fixed BPF

Signal path cables, SMA or BNC with BNC-to-SMA adapters

6 dB 50-

Ω

attenuator

1.2

Required Software

The following software is required and available online.

To operate the ADS58J64EVM device: ADS58J64EVM_GUI_Installer.zip

To operate the TSW14J56EVM device: High Speed Data Converter Pro software

See

Section 1.4

for the software links.

Summary of Contents for ADS58J64 EVM

Page 1: ...ation Results 10 3 1 ADS58J64 Operating Mode 10 3 2 LMK04828 Clocking Configuration 11 3 3 Using an External Clock 11 3 4 Using a Coherent Input Source Frequency 12 3 5 HSDC Pro Settings 12 4 Software...

Page 2: ...017 Submit Documentation Feedback Copyright 2017 Texas Instruments Incorporated ADS58J64 EVM 7 Low Level View Controls 14 8 Jumper and Button Descriptions and Default Settings 16 9 Connector Descripti...

Page 3: ...Evaluation Board EVM Mini USB cable The EVM evaluation kit does not include the following list of equipment but these items are required for evaluation of this product to achieve the best performance...

Page 4: ...is the starting point for all evaluations 2 1 Software Installation The proper software must be installed before beginning the evaluation See Section 1 2 for a list of the required software Section 1...

Page 5: ...and follow the installation prompts 2 2 Hardware Setup Procedure Figure 2 shows a typical test setup using the ADS58J64EVM and TSW14J56EVM REV D devices This test setup is used for the quick start pro...

Page 6: ...attenuator 11 Place the bandpass filter between the analog signal generator and the attenuator input to remove noise and harmonics from the signal generator 12 Turn on all signal generators 2 3 Softw...

Page 7: ...ro Figure 3 shows the GUI main page Figure 3 HSDC Pro GUI Main Panel Figure 4 HSDC Pro Sampling Rate and Additional Device Parameters 2 When prompted to select the capture board select the TSW14J56 wh...

Page 8: ...Capture in HSDC Pro to capture data from the ADC 10 In HSDCPRO change the Test Selection to Single Tone 11 Also in HSDCPRO change the spectrum analysis from Real FFT to Complex FFT 12 From the Test O...

Page 9: ...e an LED status update Device GUI is not working properly Verify that the USB cable is plugged into the EVM and the PC Check the Device Manager of the computer and verify that a USB Serial Device is r...

Page 10: ...quency HSDC Pro ADC Sampling Rate Decimation NCO Mode 0 983 04 MHz 491 52M 2 122 88M 737 28 MHz 368 64M 2 92 16M Mode 1 983 04 MHz 491 52M 2 Depends on programmed NCO word 737 28 MHz 368 64M 2 Depends...

Page 11: ...ock The LMK04828 device provides a very low noise device clock but the noise performance may not be as good as a premium bench RF signal generator so the measured noise performance of the ADS58J64 dev...

Page 12: ...performance measurements Table 5 HSDC Pro Options for Optimal Analysis Results HSDC Pro Feature Description Analysis window samples Selects the number of samples to include in the selected test analys...

Page 13: ...Descriptions Tab Description INTRO Quick configuration of the devices on the EVM for evaluation ADS58J64 Mode Provides DDC Mode control for the ADS58J64 ADS58J64 Other Provides additional functionalit...

Page 14: ...er highlighted in the Register Map with the value in the Write Data field This button must be clicked after changing bits in the register data section Write All button Update all registers shown in th...

Page 15: ...7 Texas Instruments Incorporated ADS58J64 EVM 5 EVM Hardware Modifications from Default The following hardware changes are required for proper operation of the ADS58J64EVM Rev A default PCB built and...

Page 16: ...t 2 3 Force as logic LOW normal operation NOTE Open is not a valid state for this jumper JP3 SPI Select CPLD Short 2 3 Short 1 2 Reserved Do not use this state Short 2 3 Default state NOTE Open is not...

Page 17: ...SPI OPEN Pin1 SCK Pin2 SEN Pin3 SDIO Pin4 SDO J14 JTAG Programming Header for CPLD U3 OPEN Pin1 TCK Pin3 TDO Pin4 1 8 V Pin5 TMS Pin9 TDI Pin2 Pin10 GND A 2 Connector Descriptions Table 9 lists the EV...

Page 18: ...escriptions LED Description PWR D2 Indicates status of input power OFF Power is not provided at J14 ON Power is provided at J14 CLKIN0 SEL D4 Not functional CLKIN1 SEL D5 Not functional PLL1 LOCKED D6...

Page 19: ...TI Resource NO OTHER LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY RIGHT OF TI OR ANY THIRD...

Page 20: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Texas Instruments ADS58J64EVM...

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