Texas Instruments ADS54J54EVM, User Manual

Page: 3 / 22

www.ti.com
Introduction
Table 1. Input and Output Connectors and Jumper Descriptions of the
ADS54J54EVM
Component Description
J1 (AINP) Analog input for channel A, single-ended or positive side of differential.
(Negative side of differential on J11, normally not installed.)
J2 (BINP) Analog input for channel B, single-ended or positive side of differential.
(Negative side of differential on J12, normally not installed.)
J23 (CINP) Analog input for channel C, single-ended or positive side of differential.
(Negative side of differential on J25, normally not installed.)
J22 (DINP) Analog input for channel D, single-ended or positive side of differential.
(Negative side of differential on J24, normally not installed.)
J19 (EXT_ADC_CLK) Single-ended ADC clock input
J20 DCLK Optional device clock output, single-ended transformer coupled
J8 (+5V) Positive power connection (5 V)
J9 (GND) Negative power connection (GND)
J13 (Main PWR) 5-V input from +5-V bench supply (cable supplied)
J14 (REF OSC_IN) External reference option for LMK04828, REFOUT1 source on J16 and
CPLD_CLK
J16 (REFOUT1) 10-MHz CMOS level reference output or frequency of REF OSC_IN if
option selected
J6 (USB) USB connection
J3 JESD204B FMC interface connector
J5 (TRIG_IN) External trigger input for ADS58J89 burst mode. Not used for ADS54J54.
J26 (TRIG_OUT) Trigger output, buffered version of ADS58J89 burst mode trigger, normally
connected to trigger input of TSW14J56 capture card. Normally not used for
ADS54J54.
J7 (LMK CLKIN1_P) CLKIN0 input for LMK04828. Option to provide an external clock source to
the LMK in place of on-board 100-MHz VCXO.
J10 (CLKOUT6P) DCLKOUT6p from LMK04828. Default is LVPECL at 250 MHz.
J15 (CLKOUT6N) DCLKOUT6n from LMK04828. Default is LVPECL at 250 MHz.
J17 (CLKOUT7P) SDCLKOUT7p from LMK04828. Default is LVPECL at 6.25 MHz.
J4 (CLKOUT7M) SDCLKOUT7m from LMK04828. Default is LVPECL at 6.25 MHz.
J18 (PROG CPLD) JTAG interface for CPLD U3
SW1 (ADC_RESET) Switch to reset the ADC using the RESET input pin
SW2 (TRIGGER) Pushbutton trigger source for ADS58J89 burst mode. Not used for
ADS54J54.
JP6 (XO_PWR) Provides power to VCXO Y2 or oscillator Y3
SJP3 (REF_SEL) Selects input or external reference source for LMK, J16 and CPLD. Default
is internal (on-board) 10-MHz oscillator.
JP2 (CDC_CLK) Reference clock buffer output enable
JP5 (REF_PWR) Power enable for 10-MHz reference oscillator
SJP1 (REF_EN) Enable for 10-MHz reference oscillator
SJP4-SJP11 USB/FMC Interface select. Default is using USB.
JP4 (ENABLE) U11 enable. Install jumper to disable switcher U11. Default is uninstalled.
JP1 (PWRGD) Test point for power good output pin from U11.
3 SLAU616A – January 2015 – Revised January 2016 ADS54J54 Evaluation Module
Submit Documentation Feedback
Copyright © 2015–2016, Texas Instruments Incorporated