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Optional Configurations
J11 and J13 are the power supply for THS4509. An on-board layout option for a LPF or BPF is available
between the amplifier and the ADC. By default the filter is bypassed to allow the user flexibility to design
according to desired specifications.
3.2
On-Board CDC72010 Clock
The default clock input configuration is 1:4 transformer coupling through T6. The optional configuration is
through clock driver CDC72010. The changes required to modify the transformer coupled clock input to
clock driver input are shown in
.
Table 4. Jumper Setting for Transformer-Coupled or CDC72010 Input
Jumper
Transformer-Coupled (Default)
CDC72010
J14
shunt
open
JP20
Shunt 1 2
Shunt 1 2
JP21
Shunt 1 2
Shunt 1 2
J18
open
open
R121
0 ohm
DNI
R122
DNI
0 ohm
SJP7
Short 1 2
Short 3 4
SJP6
Short 3 4
Short 5 6
The on-board layout is available for the option of VCXO and crystal BPF. The CDCE72010 comes with a
default configuration (see CDCE72010 data sheet (
) for details about device default
configuration). With a 10MHz primary reference at J19 and a 983.04 MHz VCXO on-board the CDC
outputs a LVCMOS clock at U0P (pin7) at 245.76MHz. With a 491.52 MHz VCXO the CDC outputs a
LVCMOS clock at U0P at 122.88MHz. The clock goes through an on-board crystal BPF (Y0) and is used
as the input clock to the ADC through SJP6.
3.3
Parallel CMOS Output
The default ADC output is configured as DDR LVDS output on the EVM. The layout provides an option of
1.8v parallel CMOS output from the ADC. The changes required to modify from DDR LVDS output to
parallel CMOS output are shown in
Table 5. Jumper/Component Setting for DDR LVDS Output and Parallel CMOS
Output
Jumper/Component
DDR LVDS Output
Parallel CMOS
U12 (SN74AVC16T245)
DNI
Installed
U13 (SN74AVC16T245)
DNI
Installed
RN5 to RN8
Installed
DNI
RN9 to RN12
Installed
DNI
JP26
Open
Shunt
JP27
Open
Shunt
The CMOS output data is output from the EVM board at 40-pin connectors J1 (ch A) and J2 (ch B).
9
SLAU333 – March 2011
ADS42xx EVM
© 2011, Texas Instruments Incorporated
