Texas Instruments ADS131B26Q1EVM-PDK, User Manual

Page: 29 / 36

7.3 Schematics
Figure 7-7 and Figure 7-8 contain the schematics for the ADS131B26Q1EVM-PDK.
AVDD
40
IO VDD
34
GPIO0 / MHD
33
GPIO1
26
GPIO2/F AULT
25
GPIO3/ OCCA
24
GPIO4/ OCCB
22
CS
31
DRDY
27
RESET
23
APWR
38
CLK
32
CNA
6
CNB
9
CPA
5
CPB
10
DCAP
36
DPWR
37
RCAPA
41
RCAPB
20
SCLK
28
SDI
30
SDO
29
Thermal_ Pad
49
V0A
2
V0B
11
V1A
1
V1B
12
V2A
48
V2B
13
V3A
47
V3B
14
V4A
46
V4B
15
V5A
45
V5B
16
V6A
44
V6B
17
V7A
43
V7B
18
VNA/ GPI O1A
4
VNB/G PI O1B
7
VPA/ GPI O0A
3
VPB/G PI O0B
8
AGND
21
AGND
39
AGNDA
42
AGNDB
19
DGND
35
ADS131B26QPHPRQ1
U2
ADC_APWR
ADC_DPWR
AGND
1µF
C19 AGND
1µF
C18
AGND
DGND
DGND
AGND
1µF
C22
1µF
C28
1µF
C25
1µF
C23
ADC_AVDD
ADC_IOVDD ADC_DPWR
ADC_APWR
AGND
DGND DGND
AGND
V0A
V1A
V2A
V3A
V4A
V5A
V6A
V7A 2200pF
C8
SCLK
SDI
SDO
CS
DRDY
RESET
GPIO0/MHD
GPIO1
GPIO2/FAULT
GPIO3/OCCA
GPIO4/OCCB
CLK
ADC DIGITAL
TMP6131QLPGMQ1
R18
AGND
V_TMP61
RCAPA
RCAPB
0
R31
V0A
ADC_DIGITAL
ADC_APWR
AGND
ADC_DPWR
DGND
ADC_AVDD VADC_HV
ADC_IOVDD
0 R71
DNP
DGND
0
R27
0
R28
100
R8
100
R19
0.047uF
C5
AGND
RCAPA
1
2
3
JP1
TMP61_VBIAS
ADC_AVDD
TP5
VNA/GPIO1A
TP1
VPA/GPIO0A
V0B
V1B
V2B
V3B
V4B
V5B
V6B
V7B
100
R9
100 R24
0.047uF
C6
2200pF
C9
0
R29
0
R30
TP2
VPB/GPIO0B
TP6
VNB/GPIO1B
GND
1
GND
2
OUT
3
VDD
4
GND
5
LMT84QDCKRQ1
U1
AGND
AGND
V0B
ADC_AVDD
AGND
ADC2A_V3A
V3A
ADC2A_V2A
ADC2A_V3A
AGND
ADC2A_V4A
V4A
ADC2A_V6A
V6A
ADC2A_V6A
ADC2A_V7A
ADC2A_V5A
ADC2A_V4A
ADC3A_VPA
ADC3A_VNA
ADC1A_CPA
ADC1A_CNA
ADC3B_VPB
ADC3B_VNB
ADC1B_CNB
ADC1B_CPB
AGND
ADC2A_V1A
V1A
AGND
ADC2A_V2A
V2A
10.5k
R11
ADC2A_V5A
V5A
10.5k
R33
100 R20
100
R23
100nF
C3
100nF
C10
100nF
C12
100nF
C14
V7A
V7A
100nF
C16
AGND
100nF
C20
100k
R72
100k
R78
100k
R79
100k
R80
100k
R82
DGND DGND DGND DGND DGND
100k
R76
100k
R74
100k
R75
100k
R77
100k
R81
DGND DGND DGND DGND DGND
100k
R73
ADC_IOVDD
A
D
C
_
D
IG
IT
A
L
.G
P
IO
0
/M
H
D
A
D
C
_
D
IG
IT
A
L
.G
P
IO
1
A
D
C
_
D
IG
IT
A
L
.G
P
IO
2
/F
A
U
LT
A
D
C
_
D
IG
IT
A
L
.G
P
IO
3
/O
C
C
A
A
D
C
_
D
IG
IT
A
L
.G
P
IO
4
/O
C
C
B
A
D
C
_
D
IG
IT
A
L
.C
S
A
D
C
_
D
IG
IT
A
L
.S
C
L
K
A
D
C
_
D
IG
IT
A
L
.S
D
I
A
D
C
_
D
IG
IT
A
L
.S
D
O
A
D
C
_
D
IG
IT
A
L
.D
R
D
Y
A
D
C
_
D
IG
IT
A
L
.R
E
S
E
T
ADC_DIGITAL
100nF
C7
100nF
C2
AGND
0.1
R66
0.1
R57
ADC_IOVDD
ADC_AVDD
3.00k
R38
3.00k
R10
10.5k
R34
10.5k
R1
30.9k
R39
30.9k
R40
30.9k
R45
1.96k
R44
1.96k
R50
30.9k
R46
13.7k
R51
13.7k
R52
1.96k
R56
13.7k
R58
13.7k
R59
1.96k
R63
AGND
ADC2B_V3B
V3B
AGND
ADC2B_V4B
V4B
ADC2B_V6B
V6B
AGND
ADC2B_V1B
V1B
AGND
ADC2B_V2B
V2B
10.5k
R17
ADC2B_V5B
V5B
10.5k
R36
100nF
C4
100nF
C11
100nF
C13
100nF
C15
V7B
V7B
100nF
C17
AGND
100nF
C21
AGND
3.00k
R37
3.00k
R16
10.5k
R35
10.5k
R6
30.9k
R42
30.9k
R41
30.9k
R48
1.96k
R43
1.96k
R49
30.9k
R47
13.7k
R54
13.7k
R53
1.96k
R55
13.7k
R61
13.7k
R60
1.96k
R64
30.9k
R3
30.9k
R12
1.96k
R25
30.9k
R4
30.9k
R15
1.96k
R26
AGND
O
p
tio
n
a
l
e
x
te
rn
a
l
V
C
M
100nF
C26
DNP
ADC_AVDD
AGND
0
R13
AGND
0
R14
AGND
0
R22
AGND
0
R21
AGND
V7A
O
p
tio
n
a
l
e
x
te
rn
a
l
V
C
M
100nF
C27 DNP
ADC_AVDD
AGND
V7B
1.50k
R7
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15
17
19
21
23
16
18
20
22
24
J7
DEBUG
ADC_DIGITAL.GPIO0/MHD
ADC_DIGITAL.DRDY
ADC_DIGITAL.SCLK
ADC_DIGITAL.SDO
ADC_DIGITAL.SDI
ADC_DIGITAL.CS
ADC_DIGITAL.GPIO1
ADC_DIGITAL.GPIO2/FAULT
ADC_DIGITAL.GPIO3/OCCA
ADC_DIGITAL.RESET
ADC_DIGITAL.GPIO4/OCCB
DGND
ADC_DIGITAL.GPIO0/MHD
ADC_DIGITAL.DRDY
ADC_DIGITAL.SCLK
ADC_DIGITAL.SDO
ADC_DIGITAL.SDI
ADC_DIGITAL.CS
ADC_DIGITAL.GPIO1
ADC_DIGITAL.GPIO2/FAULT
ADC_DIGITAL.GPIO3/OCCA
ADC_DIGITAL.RESET
ADC_DIGITAL.GPIO4/OCCB
DGND
ADC3A_VNA
ADC1A_CPA
ADC1A_CNA
ADC2A_V1A
ADC2A_V0A
ADC3A_VPA
J6
J8
1
2
3
4
5
6
J5
1
2
3
4
5
6
J1
1
2
3
4
5
6
J3
ADC3B_VNB
ADC3B_VPB
ADC1B_CNB
ADC1B_CPB
ADC2B_V0B
ADC2B_V1B
1
2
3
4
5
6
J4
ADC2B_V2B
ADC2B_V6B
ADC2B_V7B
ADC2B_V3B
ADC2B_V5B
ADC2B_V4B
220nF
C24
0
R5
DNP
ADC2B_V0B
0
R32
DNP
ADC2A_V0A
J2
AGND
NT1
Net-Tie
AGND DGND
TP3 TP4
AGND
TP7
DGND
TP9
ISO_GND
0
R62
DNP
ADC2A_V7A
0
R65
DNP
ADC2B_V7B
VADC_HV
1
2
3
JP3
DIGITAL ADC SUPPLY
ADC_DPWR
1
2
3
JP2
ANALOG ADC SUPPLY
ADC_APWR
10nF
C1
10.0k
R69
DNP
10.0k
R70
DNP
10.0k
R67
DNP
10.0k
R68
DNP
10.0k
R2
Vin = 0 V to 10 V
Default Gain = 4
DCAP between pins 35-36
RCAPA between pins 41-42
RCAPB between pins 19-20
Default setting: [2-3]
To bypass internal LDOs, short [1-2] and
provide external voltage using terminal blocks.
-40C to 150C = 1.247 V to 183 mV
ADC2 inputs:
Unipolar
ADC2y_V1y/2y
Gain = 1
0V to 10V
Bipolar
ADC2y_V3y/4y
Gain = 4
-10V to +10V
Pseudo-diff
ADC2y_V5y/6y
Gain = 2
-8.5V to +10V
Vin = 0 V to 10 V
Default Gain = 4
Figure 7-7. Analog Inputs, ADC Power, and Interface Connections
www.ti.com ADS131B26Q1EVM-PDK Bill of Materials, PCB Layout, and Schematics
SBAU413 – OCTOBER 2022
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