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Using the Software: ADS1299 Control Registers and GUI

5.5.1

Lead-Off Sense (LOFF_SENSP and LOFF_SENSN) Registers

These registers enable lead-off detection for both the positive and negative channels.

describes

the 4-bit DAC settings to configure the lead-off threshold. Note that the LOFF_FLIPx bits change the
direction of the lead-off current if this option is selected.

illustrates the connections from the

positive and negative inputs to the lead-off comparators.

shows the respective GUI panel on the

EVM software.

Figure 24. LOFF_STATP and LOFF_STATN Comparators

Figure 25. LOFF_SENSP and LOFF_SENSN Registers GUI Panel

24

EEG Front-End Performance Demonstration Kit

SLAU443 – May 2012

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Copyright © 2012, Texas Instruments Incorporated

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Summary of Contents for ADS1299

Page 1: ...es Not Supported in Current Version 5 2 4 ADS1299EEG FE Hardware 5 2 5 Factory Default Jumper Settings 6 3 Software Installation 7 3 1 Minimum Requirements 7 3 2 Installing the Software 7 3 3 Install...

Page 2: ...er 12 13 ADS1299 EEG FE Front End Block Diagram 14 14 Input Configurations Supported by the EEG FE a Differential Inputs b Single ended inputs 17 15 File Save Option Under Save Tab 18 16 Channel Regis...

Page 3: ...Noise for Input Short with 5k Resistors 45 55 MISC1 Register Setting for SRB1 46 56 Noise with Negative Input Connected to SRB1 Pin 47 57 Noise with OPA376 in SRB1 Path 48 58 Scope Tab with Sinusoidal...

Page 4: ...o are familiar with the risks associated with handling electrical and mechanical components systems and subsystems You are responsible for the safety of yourself your fellow employees and contractors...

Page 5: ...ware Features Configurable for bipolar or unipolar supply operation Configurable for internal and external clock and reference via jumper settings Configurable for dc coupled inputs External bias elec...

Page 6: ...d to external reference generation circuitry JP4 1 2 5V supply to board JP5 Not Installed Option to provide hardware PWDN signal JP6 1 2 BIAS_ELEC to onboard midsupply JP7 1 2 Route REF_ELEC to buffer...

Page 7: ...ible input Hard disk drive with at least 200MB free space Microsoft Windows XP operating system with SP2 Windows Vista and Windows 7 are NOT supported at this time Mouse or other pointing device 1280...

Page 8: ...FE You must accept the license agreement shown in Figure 4 before you can proceed with the installation Figure 4 License Agreement 8 EEG Front End Performance Demonstration Kit SLAU443 May 2012 Submi...

Page 9: ...nstallation Figure 5 Installation Process Figure 6 USBStyx Driver Preinstallation 9 SLAU443 May 2012 EEG Front End Performance Demonstration Kit Submit Documentation Feedback Copyright 2012 Texas Inst...

Page 10: ...wall mount power supply and connect the MMB0 to your PC via any available USB port There are two USB drivers which will be installed Follow the steps shown in the figures below to install the USB dri...

Page 11: ...d Screen 3 Click Next and allow the wizard to find and install the driver Figure 10 Completion of the Initial USB Drive 11 SLAU443 May 2012 EEG Front End Performance Demonstration Kit Submit Documenta...

Page 12: ...downloading firmware to the processor on data capture card MMB0 Once the firmware is loaded and running it will cause the USB to re enumerate Figure 11 Second New Hardware Wizard Click Next Figure 12...

Page 13: ...d with the TI MMB0 data converter evaluation platform The key features of the ADS1299 system on a chip SOC are Eight integrated INAs and eight 24 bit high resolution ADCs Low channel noise of 1uVpp fo...

Page 14: ...tor J4 All other power supplies needed for the front end board are generated on board by power management devices The EVM is shipped in 5V unipolar supply configuration The ADS1299 can operate from 5...

Page 15: ...it that generates a 2 048MHz clock nominal This clock can vary by 5 over temperature For applications that require higher accuracy the ADS1299 can also accept an external clock signal The ADS1299EEG F...

Page 16: ...bal Registers control tab refer to Section 5 2 to calculate the input referred voltage value for all the tests The default value is 4 5V If any other value is used the user must update this field in t...

Page 17: ...mode range of the PGA If the input differential signal is centered around 0V the ADS1299 needs to be operated with a bipolar supply Refer to Section 4 1 for details on setting the EVM to operate with...

Page 18: ...nation of channels to be saved in a given directory location with notes to describe the saved data Figure 15 shows the Save tab options Figure 15 File Save Option Under Save Tab 5 1 Overview and Featu...

Page 19: ...nd the bias reference and the Lead Off Control Register controls the comparator threshold and the magnitude and frequency of the lead off signal shows the GUI panel to manipulate these registers and t...

Page 20: ...om Figure 17 Input Multiplexer for a Single Channel MAIN 000 or 110 or 111 Figure 18 Channel Control Registers GUI Panel 20 EEG Front End Performance Demonstration Kit SLAU443 May 2012 Submit Document...

Page 21: ...signals may be viewed on the Analysis Scope tab as Figure 20 shows Detailed instructions for using the Analysis Scope tab is provided in Section 6 1 1 Figure 20 Internal Test Signals 5 3 2 Temperatur...

Page 22: ...is Scope tab as shown in Figure 22 The number 0 146V on the y axis can be calculated as a temperature using Equation 1 Temperature 0 146 0 145300 0 00049 25 26 4 C It should be noted that the temperat...

Page 23: ...libration test signal to ADS1299 device without connecting the calibration test signal to the electrodes The positive signal can be applied to BIASIN pin and the negative input can be applied to the B...

Page 24: ...e LOFF_FLIPx bits change the direction of the lead off current if this option is selected Figure 24 illustrates the connections from the positive and negative inputs to the lead off comparators Figure...

Page 25: ...the lead off registers The GUI shows when a lead is disconnected by turning its bit from green to red Figure 26 illustrates the Lead Off Status Registers GUI controls Figure 26 Lead Off Status Indica...

Page 26: ...ter Map Device Registers tab is a helpful debug feature that allows the user to view the state of all the internal registers This tab is illustrated in Figure 28 Figure 28 Device Register Settings 26...

Page 27: ...f the measured input signals from each channel Additionally users can determine the noise contribution from each channel at a given resolution and review the sampling rate the PGA gain and the input s...

Page 28: ...ent amplitudes of the EEG waveform harmonics Figure 31 illustrates the histogram output for input short on all channels The same Signal Zoom analysis may be used on the histogram plots for a more deta...

Page 29: ...annel specific spectrum as well as typical figures of merit such as SNR THD ENOB and CMRR Each feature is numbered below and described in detail in the following subsections Figure 32 illustrates an A...

Page 30: ...The Ideal AIN Frequency is a value that is calculated based on the sampling rate such that the coherent sampling criteria can be met AC Analysis Parameters 2 This section of the tool allows the user...

Page 31: ...the channel to channel noise Figure 34 Analysis FFT FFT Analysis Input Short Condition User Defined Dynamic Range 4 This section enables the user to examine the SNR of a specific channel within a giv...

Page 32: ...BIAS_ELEC REF_ELEC available at the connector JP81 that correspond to these two electrodes The BIAS_DRV signal is similar to the BIAS_ELEC but appears as a separate signal at JP80 In future versions o...

Page 33: ...amplifier The table below shows the jumper settings for the two options Table 9 Dedicated Reference Drive Options through REF_ELEC JP7 JP8 Un Buffered Don t care 1 2 Buffered 1 2 2 3 Bias There is an...

Page 34: ...37 channel 7 is used as a bias electrode 7 1 3 Biasing the Patient with a Feedback Loop There are two options on the EVM board to bias the patient First option is to use onboard BIAS_ELEC signal to dr...

Page 35: ...the application requires the common mode to be set to any other voltage this configuration can be accomplished by setting the appropriate bit in the Configuration 3 Register The external BIASREF volt...

Page 36: ...o analyze the input signal If the input signal is dc coupled the dc lead off scheme can be used If the input signal is ac coupled the ac lead off scheme must be used When using the dc lead off scheme...

Page 37: ...has an option where the LOFF_STATP and LOFF_STATM Registers are continuously polled set the Read Status Registers switch as shown in shown in Figure 43 This option allows the user to see the lead off...

Page 38: ...he inputs depends on the impedance on each electrode and the current used for lead off detection If we denote the source impedance on INP pin as Zinp and the source impedance on INM pin as Zinm the pe...

Page 39: ...rently with the EEG measurement Figure 46 shows the fft result of AC lead off detection at fDR 4 with data rate of 4Ksps The impedance component is present at 1KHz and must be bandpass filtered The EE...

Page 40: ...es not appear at a jumper needs to be soldered to one side of R5 7 3 1 Channel Inputs Disconnected It may sometimes be required to provide a calibration or test signal to ADS1299 channel without the s...

Page 41: ...to the pin or electrode This can be accomplished by connecting the positive test signal to SRB2 pin and the negative test signal to SRB1 pin The channel input multiplexer must be set for Normal Electr...

Page 42: ...tive test signal must be tied to SRB2 pin and the negative test signal must tie to BIASIN pin The channel multiplexer must be set for 111 and the SRB2 switch must be closed This multiplexer setting is...

Page 43: ...hannel It also gives the offset in the channel The result can be seen in the analysis tab Figure 52 shows a snapshot of the scope for internal input short with gain setting of 24 The channel offset in...

Page 44: ...e source present are two 5K resistors in the input path and the channel noise This test is useful to measure the effect of input bias current on noise The PGA in ADS1299 has CMOS input and thus has ne...

Page 45: ...Register Settings for External Input Short Test Figure 54 Scope Showing Noise for Input Short with 5k Resistors 45 SLAU443 May 2012 EEG Front End Performance Demonstration Kit Submit Documentation Fee...

Page 46: ...required These settings routes the common mode voltage VCM on BIAS_ELEC to all the positive inputs It also connects BIAS_ELEC to REF_ELEC via R11 5K REF_ELEC is connected to SRB1 pin on ADS1299 The n...

Page 47: ...Options on the EVM Figure 56 Noise with Negative Input Connected to SRB1 Pin 47 SLAU443 May 2012 EEG Front End Performance Demonstration Kit Submit Documentation Feedback Copyright 2012 Texas Instrume...

Page 48: ...pers 3 4 and 5 6 are required On JP8 a jumper 2 3 is required and on JP7 a jumper 1 2 is needed The GUI settings are same as in Figure 56 Figure 57 shows a snapshot of the noise with SRB1 driven by a...

Page 49: ...inputs can be found in Section 5 3 8 6 Arbitrary Input Signal Any input signal can be fed to the device on connector J6 as described in Section 4 6 Figure 58 shows the results obtained when a single...

Page 50: ...O4 46 DRDY 47 DVDD 48 DGND 51 AVSS 32 DVDD 50 DGND 49 CLKSEL 52 AVSS1 53 AVDD1 54 VCAP3 55 AVDD 59 AVDD 56 AVSS 23 AVSS 57 AVSS 58 AVDD 19 AVDD 21 BIASIN 62 BIASINV 61 BIASOUT 63 RESV1 31 AVDD 22 BIAS...

Page 51: ...C BIAS_SHD AGND 1 2 3 4 5 AIN1 R10 4 99K R11 4 99K C75 4 7nF AGND R12 4 99K 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 J6 36PIN_IDC 1 2 3 4 5 6...

Page 52: ...2 2uF L5 3 3uH C61 10uF C60 10uF EN 3 NR FB 4 OUT 5 GND 2 IN 1 U9 TPS73225 R56 NI R57 NI C58 1uF TP13 EN 3 NR FB 4 OUT 5 IN 2 GND 1 U8 TPS72325 AGND AGND AGND AGND AGND 2 5V 2 5V AGND AGND AGND AGND A...

Page 53: ...18 19 20 J2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 J3 1 2 3 4 5 6 7 8 9 10 J4 R51 NI VREFP R50 NI C40 NI 3 2 6 7 4 8 U5 NI AVDD AVSS R47 NI C38 NI C39 NI R48 NI C42 NI C41 NI R49 NI JP3 NI...

Page 54: ...chematics www ti com Figure 64 ADS1299EEG FE Top Assembly Figure 65 ADS1299EEG FE Top Layer 54 EEG Front End Performance Demonstration Kit SLAU443 May 2012 Submit Documentation Feedback Copyright 2012...

Page 55: ...and Schematics Figure 66 ADS1299EEG FE Internal Layer 1 Figure 67 ADS1299EEG FE Internal Layer 2 55 SLAU443 May 2012 EEG Front End Performance Demonstration Kit Submit Documentation Feedback Copyright...

Page 56: ...matics www ti com Figure 68 ADS1299EEG FE Bottom Layer Figure 69 ADS1299EEG FE Bottom Assembly 56 EEG Front End Performance Demonstration Kit SLAU443 May 2012 Submit Documentation Feedback Copyright 2...

Page 57: ...SM 110 01 T DV P 2 J2 J3 Bottom 10 Pin Dual Row SM Header 20 Pos Samtec SSW 110 22 F D VS K 1 J4 Bottom 5 Pin Dual Row SM Header 10 Pos Samtec SSW 105 22 F D VS K 0 J5 Not Installed 1 J6 18 Pin Dual R...

Page 58: ...urements 0 U2 Not Installed 0 U3 U5 Not Installed 2 U4 U11 IC OP AMP GP 5 5MHZ SGL 8SOIC TI OPA376AID 0 U4A U11A Not Installed 1 U6 IC UNREG CHRG PUMP V INV SOT23 5 TI TPS60403DBVT 1 U8 IC LDO REG NEG...

Page 59: ...vided in the EVM kit makes the ADS1299EEG FE more susceptible to 50Hz 60Hz noise pickup therefore for best performance it is recommended to power the ADS1299EEG FE with a battery source This configura...

Page 60: ...ncy energy and has not been tested for compliance with the limits of computing devices pursuant to part 15 of FCC or ICES 003 rules which are designed to provide reasonable protection against radio fr...

Page 61: ...na type and its gain should be so chosen that the equivalent isotropically radiated power e i r p is not more than that necessary for successful communication This radio transmitter has been approved...

Page 62: ...roduct only after you obtained the license of Test Radio Station as provided in Radio Law of Japan with respect to this product or 3 Use of this product only after you obtained the Technical Regulatio...

Page 63: ...property damage personal injury or death If there are questions concerning these ratings please contact a TI field representative prior to connecting interface electronics including input power and in...

Page 64: ...ncy energy and has not been tested for compliance with the limits of computing devices pursuant to part 15 of FCC or ICES 003 rules which are designed to provide reasonable protection against radio fr...

Page 65: ...na type and its gain should be so chosen that the equivalent isotropically radiated power e i r p is not more than that necessary for successful communication This radio transmitter has been approved...

Page 66: ...roduct only after you obtained the license of Test Radio Station as provided in Radio Law of Japan with respect to this product or 3 Use of this product only after you obtained the Technical Regulatio...

Page 67: ...property damage personal injury or death If there are questions concerning these ratings please contact a TI field representative prior to connecting interface electronics including input power and in...

Page 68: ...egulatory and safety related requirements concerning its products and any use of TI components in its applications notwithstanding any applications related information or support that may be provided...

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