Texas Instruments ADS1285EVM-PDK, User Manual, Page: 8 / 40

3.2 ADC Input Clock (CLK) Options
Using the onboard oscillator, clock dividers, and external connectors, the ADS1285EVM-PDK has device
configuration flexibility. The ADC operates from CLK, which generates the modulator clock (f
MOD
), provided
in one of two ways:
• A crystal oscillator and the accompanying clock dividers can provide a selectable frequency for the entire
range of the ADC.
– The onboard crystal oscillator (Y1) provides the nominal 8.192-MHz clock frequency (default)
– The dividers (U6) step down the frequency to 4.096 MHz
– J8 allows the user to select between these frequencies and connect them directly to CLK by using a shunt
• An external main clock can be provided to a subminiature version A (SMA) connector (J5) or to pins 4 or 2 of
J7 when a shunt does not select the frequency from the crystal oscillator.
– In this case, a shunt must not cover J7 so that CLK is connected to any of the crystal oscillator signals
– Be sure to review the valid CLKIN input frequency in the data sheet
Note
All clock sources are sourced back to the PHI connector (J6) so that the GUI SCLK communication is
synchronous with CLK.
Figure 3-2 shows a schematic for the clock source.
1) FPGA provides CLK output
2) External oscillator drives CLK (default)
CLK Options:
Q
4
D
1
CLK
2
GND
3
VCC
5
U6
SN74AUP1G80DCKT
GND
GND
1
2
J8
GND
GND
DVDD
On-board clock
GND
Connect jumper across to
select ADC clock frequency.
DNI if using FPGA clock.
Supply range: 1.71V - 3.63V
8 MHz
4 MHz
1
2 3 4 5
J5
GND
External clock
DAC_4MHZ
Gnd
2
Output
3
Tri-state
1
Vdd
4
Y1
ECS-2520MVLC-081.92-BN-TR
DVDD
0
R31
0.1uF
C21
0.1uF
C23
100k
R30
49.9 R29
1 2
3 4
J7
CLK DIS
Figure 3-2. CLK Source (Schematic)
EVM Analog Interface www.ti.com
8 ADS1285EVM-PDK Evaluation Module SBAU394A – APRIL 2022 – REVISED SEPTEMBER 2022
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