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Table 5-1. Programmable LDO Configurations
V
OUT
3P2V
1P6V
0P8V
0P4V
0P2V
0P1V
2.5
—
—
Installed
—
Installed
Installed
3.0
—
Installed
—
—
—
—
3.3
—
Installed
—
—
Installed
Installed
4.5
—
Installed
Installed
Installed
Installed
Installed
5.0
Installed
—
—
Installed
—
—
(1)
Installed = Solder a 0-Ω jumper to GND/AVSS.
(2)
V
OUT
= 1.4 V + Σ (all grounded pins).
The PGA positive analog supply of the ADC, AVDD1, is powered by the TPS7A4701 or TPS7A4700 (U2)
onboard the EVM, which is a low-noise linear regulator that uses the 5.5-V supply on the PHI to generate a
cleaner 5-V output. The TPS47A470x is a configurable LDO so R8 to R13 can be used to change the voltage.
AVDD2 is the modulator analog supply that is also used by the ADC. As with AVDD1, AVDD2 is generated by
the TPS7A470x (U3) onboard the EVM, which is a low-noise linear regulator that uses the 5.5-V supply on the
PHI to generate a cleaner 5-V output. The TPS7A470x is a configurable LDO so R14 to R19 can be used to
change the voltage but a lower AVDD2 will result in lower THD performance in unipolar mode.
AVSS+5V is used for the analog supply of the DAC1282. This pin also uses a TPS7A470x (U4) onboard the
EVM, which is a low-noise linear regulator that uses the 5.5-V supply on the PHI to generate a cleaner 5-V
output. The DAC1282 requires a 5-V supply so R20 to R25 must not be modified.
The user has the option to configure the EVM for unipolar supplies (AVSS = 0 V) by placing a jumper to cover
pins 1 and 2 of J4 (UNIPOL), or to configure the EVM for bidirectional supplies (AVSS = –2.5 V) by placing the
jumper to cover pins 2 and 3 of J4 (BIPOL). The TPS7A3001 (U5) is an LDO with a V
IN
range from –3 V to –36
V that provides a clean –2.5-V output for the AVSS voltage. However, an external voltage is needed to supply
the AVSS voltage, which can be supplied using J3. Because AVDD1 is referenced to AVSS, the output AVDD1
must be modified using R8 to R13 so that the AVDD1 to AVSS voltage does not go above the recommended
operating conditions.
shows the supply selection and –2.5-V generation circuit.
GND
GND
AVSS
-2.5V
BIPOL
UNIPOL
TPS7A3001DRBR
OUT
1
FB
2
NC
3
GND
4
EN
5
NR/SS
6
DNC
7
IN
8
PAD
9
U5
-2.5V
GND
11.3k
R27
10.0k
R28
GND
10uF
C17
GND
10uF
C19
GND
1
2
3
J4
AVSS supply
Header for connecting an
external negative supply
source, when configuring
AVSS to -2.5V
1
2
J3
Header to select AVSS potential
(UNIPOL = GND, BIPOL = -2.5V)
GND
-IN
-2.5V
-IN
GND
AVSS
10nF
C18
10nF
C20
0
R26
Figure 5-2. ADS1285EVM-PDK Unipolar and Bidirectional Supplies Selection (Schematic)
AVDD1 is used as the supply for the
, which is a high-precision voltage reference with an integrated
high-bandwidth buffer in reference to AVSS. The voltage reference can be used to supply the positive reference,
VREFP, for the ADC and DAC using R38 as a pass transistor. Alternatively, R38 and R42 can be depopulated so
the positive and negative reference externally using pins 1 and 2 of J10, respectively.
Power Supplies
SBAU394A – APRIL 2022 – REVISED SEPTEMBER 2022
ADS1285EVM-PDK Evaluation Module
11
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