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Texas Instruments ADS1285EVM-PDK User Manual Download Page 28

9.3 Schematics

Figure 9-7

 shows a block diagram of the ADS1285EVM-PDK.

ADS1285EVM

Inputs

ADC

DAC

Reference

Power

PHI (FPGA motherboard)

Interface

The following schematic pages map to specific blocks represented in the block diagram above.

This EVM is intended to connect to a separate FPGA motherboard (not shown)

PHI Connec

t

or

Figure 9-7. ADS1285EVM-PDK Block Diagram

ADS1285EVM-PDK Bill of Materials, PCB Layout, and Schematics

www.ti.com

28

ADS1285EVM-PDK Evaluation Module

SBAU394A – APRIL 2022 – REVISED SEPTEMBER 2022

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Copyright © 2022 Texas Instruments Incorporated

Summary of Contents for ADS1285EVM-PDK

Page 1: ...ter ADC The EVM allows evaluation of all aspects of the ADS1285 This manual covers the operation of the ADS1285EVM PDK Throughout this document the terms evaluation board evaluation module and EVM are...

Page 2: ...tion Schematic 10 Figure 5 2 ADS1285EVM PDK Unipolar and Bidirectional Supplies Selection Schematic 11 Figure 5 3 Voltage Reference Schematic 12 Figure 7 1 ADS1285EVM PDK Jumper Default Settings 13 Fi...

Page 3: ...Default Shunt Settings 13 Table 7 2 Nominal Voltages Resulting From a Default Configuration 14 Table 9 1 ADS1285EVM PDK BOM 22 Trademarks LabVIEW is a registered trademark of National Instruments All...

Page 4: ...onboard crystal oscillator with dividers for 4 096 MHz Voltage supply options Unipolar or bipolar support with adjustable AVDD1 low dropout regulator LDO and externally sourced 2 5 V LDO Signals conta...

Page 5: ...specific clock input desired data rate and number of samples Then use the Capture button to collect data Section 8 1 details the EVM GUI global input parameters and the various pages within the GUI F...

Page 6: ...and R40 in combination with C30 provides the differential low pass filter used in antialiasing The series impedance is kept relatively low to maintain adequate total harmonic distortion THD performanc...

Page 7: ...R53 Place differential RC filter stages close to ADC input pins Recommended input protection TPD4E1B06DCKR Figure 3 1 Input Terminal Blocks and Headers Schematic Table 3 1 Analog Input Terminal Block...

Page 8: ...case a shunt must not cover J7 so that CLK is connected to any of the crystal oscillator signals Be sure to review the valid CLKIN input frequency in the data sheet Note All clock sources are sourced...

Page 9: ...6 General purpose I O 0 pin from the ADC DIN_PHI J6 18 SPI DIN from the ADC POCI or serial interface data in RTM GUI revision compatibility CS_ADC J6 22 SPI CS chip select or serial interface select a...

Page 10: ...F C15 5 5V GND GND GND AVDD1 supply for ADS1285 AVDD2 supply for ADS1285 AVDD supply for DAC1282 AVDD2 is referenced to the ADC s AGND 10uF C11 GND AVDD1 1 F C13 5 5V 10uF C9 AVSS AVSS AVSS AVSS AVSS...

Page 11: ...UNIPOL or to configure the EVM for bidirectional supplies AVSS 2 5 V by placing the jumper to cover pins 2 and 3 of J4 BIPOL The TPS7A3001 U5 is an LDO with a VIN range from 3 V to 36 V that provides...

Page 12: ...tortion digital synthesized voltage output designed for testing seismic equipment and the ADS128x family of devices see the DAC1282 data sheet for more information The DAC1282 can be used in combinati...

Page 13: ...l oscillator J10 Not installed Header to supply the external reference voltage to VREFN and VREFP J1 1 2 DAC PWR Connects the output of the U4 LDO AVSS 5V to the DAC analog supply pin AVDD J1 3 4 DAC...

Page 14: ...M PDK and run the GUI installer to install the EVM GUI software on your computer CAUTION Manually disable any antivirus software running on the computer before downloading the EVM GUI installer onto t...

Page 15: ...tall this driver software anyway The ADS1285EVM PDK requires the LabVIEW run time engine and may prompt for the installation of this software as shown in Figure 7 4 if not already installed Figure 7 4...

Page 16: ...m of the collected data and displays basic statistics of the result The Single Commands section allows for direct control of the device for three basic functions First the Reset button sends a signal...

Page 17: ...radio button at the Pages section of the left pane On power up the values on this page correspond to the Host Configuration Settings that enable ADC sampling at the maximum sampling rate specified fo...

Page 18: ...re 8 3 by using the Capture button The sample indices are on the x axis and there are two y axes showing the corresponding output codes as well as the equivalent analog voltages based on the specified...

Page 19: ...quired to mitigate the effects of non coherent sampling this discussion is beyond the scope of this document The 7 Term Blackman Harris window is the default option and has sufficient dynamic range to...

Page 20: ...in is adjustable in 6 dB steps and the digital gain in 0 5 dB steps The analog gain settings match those of the ADS1282 for testing at all gains with high resolution More information about each settin...

Page 21: ...te of the switches can be changed using the Switch Control drop down The settings in Figure 8 6 in combination with selecting 2 V V for PGA_GAIN and Input 2 for MUX create the time domain and spectral...

Page 22: ...6 4 0 1uF CAP CERM 0 1 uF 50 V 10 X8R AEC Q200 Grade 0 0603 603 CGA3E3X8R1H104 K080AB TDK C27 1 22uF CAP CERM 22 F 16 V 20 X5R AEC Q200 Grade 3 1206 1206 CL31A226MOHNN NE Samsung Electro Mechanics C29...

Page 23: ...utions J4 1 Header 100mil 3x1 Tin TH Header 3 PIN 100mil Tin PEC03SAAN Sullins Connector Solutions J5 1 Connector SMA TH SMA 142 0701 231 Cinch Connectivity J6 1 Header Shrouded 19 7mil 30x2 Gold SMT...

Page 24: ...03FR 071ML Yageo R62 1 37 4 RES 37 4 1 0 1 W 0603 603 RC0603FR 0737R4 L Yageo SH J1 SH J2 SH J3 SH J4 SH J5 SH J6 SH J7 SH J8 8 1x2 Shunt 100mil Gold plated Black Shunt SNT 100 BK G Samtec 969102 0000...

Page 25: ...Br DCK0005A OPA369AIDCKT Texas Instruments U10 1 ADS1285 High Resolution Delta Sigma ADC for Seismic 4000sps 1 to 64 as Gain 3 5 25V VQFN32 ADS1285IRHBT Texas Instruments None Y1 1 8 192 MHz XO Stand...

Page 26: ...er Alternate Manufacturer R51 R52 0 22 6k RES 22 6 k 1 0 1 W AEC Q200 Grade 0 0603 603 CRCW060322K6F KEA Vishay Dale ADS1285EVM PDK Bill of Materials PCB Layout and Schematics www ti com 26 ADS1285EVM...

Page 27: ...er Figure 9 3 Ground Layer 1 Figure 9 4 Power Layer Figure 9 5 Bottom Layer Figure 9 6 Bottom Silkscreen www ti com ADS1285EVM PDK Bill of Materials PCB Layout and Schematics SBAU394A APRIL 2022 REVIS...

Page 28: ...ocks represented in the block diagram above This EVM is intended to connect to a separate FPGA motherboard not shown PHI Connector Figure 9 7 ADS1285EVM PDK Block Diagram ADS1285EVM PDK Bill of Materi...

Page 29: ...CLK 22 SYNC 26 ADS1285IRHBT U10 Connects to DC127_Interface page AIN1P AIN1N AIN2P AIN2N Connects to DC127_Inputs page 1 2 3 4 5 6 J15 AVDD1 AVDD2 DVDD For IOVDD between 1 65 1 95 V CAPD must be short...

Page 30: ...1000pF C32 C0G NP0 1000pF C34 0 1uF C36 1uF C38 1 2 J14 0 R56 0 R58 22 6k R45 22 6k R46 22 6k R51 22 6k R52 1 00M R60 AVSS AVDD1 1 2 3 J12 GND 1 2 3 J13 GND 33nF 50V C35 33nF 50V C37 Vdiv NP0 1nF C30...

Page 31: ...80DCKT GND Clock dividers GND 1 2 J8 GND GND DVDD On board clock GND Connect jumper across to select ADC clock frequency DNI if using FPGA clock Configurable 1 8V or 3 3V GPIO1 GPIO0 DIN DOUT RST PWDN...

Page 32: ...OL 2 5V GND IN GND GND 2 5V IN GND 10uF C8 10uF C10 10uF C12 AVSS NOTE If you configure AVDD1 for 3 3V replace REF6241 with a REF6225 VOUT 1 4V all grounded pins 10nF C18 10nF C20 0 R26 OUT 1 NC 2 SEN...

Page 33: ...DOUT CS SW TD RESET PWDN DAC1282_SPI Connects to DC127_Interface page Connects to DC127_Reference page VREFP Digital to Analog converter DAC_SWOUTP DAC_SWOUTN Connects to DC127_ADC page DVDD AVSS AVS...

Page 34: ...11 Revision History NOTE Page numbers for previous revisions may differ from page numbers in the current version Changes from Revision April 2022 to Revision A September 2022 Page Changed document to...

Page 35: ...ther than TI b the nonconformity resulted from User s design specifications or instructions for such EVMs or improper system design or c User has not paid on time Testing and other quality control tec...

Page 36: ...These limits are designed to provide reasonable protection against harmful interference in a residential installation This equipment generates uses and can radiate radio frequency energy and if not in...

Page 37: ...instructions set forth by Radio Law of Japan which includes but is not limited to the instructions below with respect to EVMs which for the avoidance of doubt are stated strictly for convenience and s...

Page 38: ...any interfaces electronic and or mechanical between the EVM and any human body are designed with suitable isolation and means to safely limit accessible leakage currents to minimize the risk of electr...

Page 39: ...R DAMAGES ARE CLAIMED THE EXISTENCE OF MORE THAN ONE CLAIM SHALL NOT ENLARGE OR EXTEND THIS LIMIT 9 Return Policy Except as otherwise provided TI does not offer any refunds returns or exchanges Furthe...

Page 40: ...change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and display of thes...

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