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FORMAT0

DIN

Modulator Clock Output

IOVDD

SCLK

FORMAT1

FORMAT2

Modulator Data Channel 2

DOUT2

Modulator Data Channel 1

DOUT1

Modulator Data Channel 4/8

(1)

DOUT4/8

(1)

DRDY

(SPI Protocol)

DOUT

(Frame-Sync Protocol)

Internal Reset

CLK

3V nom

(1)

AVDD

1V nom

(1)

IOVDD

1V nom

(1)

DVDD

Valid Data

CLK

129 (max)

DATA

ADS1274
ADS1278

www.ti.com

SBAS367F

–

JUNE 2007

–

REVISED FEBRUARY 2011

POWER SUPPLIES

MODULATOR OUTPUT

The ADS1274/78 has three power supplies: AVDD,

The ADS1274/78 incorporates a 6th-order, single-bit,

DVDD, and IOVDD. AVDD is the analog supply that

chopper-stabilized

modulator

followed

powers the modulator, DVDD is the digital supply that

multi-stage digital filter that yields the conversion

powers the digital core, and IOVDD is the digital I/O

results. The data stream output of the modulator is

power supply. The IOVDD and DVDD power supplies

available directly, bypassing the internal digital filter.

can be tied together if desired (+1.8V). To achieve

The digital filter is disabled, reducing the DVDD

rated performance, it is critical that the power

current, as shown in

Table 16

. In this mode, an

supplies

are

bypassed

with

0.1

and

external digital filter implemented in an ASIC, FPGA,

capacitors placed as close as possible to the supply

or similar device is required. To invoke the modulator

pins. A single 10

F ceramic capacitor may be

output, tie FORMAT[2:0], as shown in

Figure 85

substituted in place of the two capacitors.

DOUT[4:1]/[8:1] then becomes the modulator data
stream outputs for each channel and SCLK becomes

Figure 84

shows the start-up sequence of the

the modulator clock output. The DRDY/FSYNC pin

ADS1274/78. At power-on, bring up the DVDD supply

becomes an unused output and can be ignored. The

first, followed by IOVDD and then AVDD. Check the

normal

operation

the

Frame-Sync

and

SPI

power-supply sequence for proper order, including

interfaces is disabled, and the functionality of SCLK

the ramp rate of each supply. DVDD and IOVDD may

changes from an input to an output, as shown in

be sequenced at the same time (for example, if the

Figure 85

supplies are tied together). Each supply has an
internal reset circuit whose outputs are summed

Table 16. Modulator Output Clock Frequencies

together to generate a global power-on reset. After

MODULATOR

the supplies have exceeded the reset thresholds, 2

CLOCK

ADS1274

ADS1278

CLK

cycles are counted before the converter initiates

MODE

OUTPUT

DVDD

the conversion process. Following the CLK cycles,

[1:0]

CLKDIV

(SCLK)

(mA)

the data for 129 conversions are suppressed by the

CLK

4.5

ADS1274/78 to allow output of fully-settled data. In

CLK

4.0

SPI protocol, DRDY is held high during this interval.

CLK

2.5

In frame-sync protocol, DOUT is forced to zero. The

power supplies should be applied before any analog

CLK

2.5

or digital pin is driven. For consistent performance,

CLK

/40

1.0

assert SYNC after device power-on when data first

CLK

0.5

appear.

(1) The ADS1274 has four channels; the ADS1278 has eight
channels.

Figure 85. Modulator Output

(1) The power-supply reset thresholds are approximate.

Figure 84. Start-Up Sequence

2007

–

2011, Texas Instruments Incorporated

Submit Documentation Feedback

Product Folder Link(s):

ADS1274 ADS1278

Summary of Contents for ADS1274

Page 1: ...drift specifications are significantly weaker Low Power 52kSPS 31mW ch than respective industrial counterparts The ADS1274 Low Speed 10kSPS 7mW ch and ADS1278 combine these types of converters Linear Phase Digital Filter allowing high precision industrial measurement with SPI or Frame Sync Serial Interface excellent dc and ac specifications Low Sampling Aperture Error The high order chopper stabil...

Page 2: ...duct folder at www ti com ABSOLUTE MAXIMUM RATINGS Over operating free air temperature range unless otherwise noted 1 ADS1274 ADS1278 UNIT AVDD to AGND 0 3 to 6 0 V DVDD IOVDD to DGND 0 3 to 3 6 V AGND to DGND 0 3 to 0 3 V Momentary 100 mA Input current Continuous 10 mA Analog input to AGND 0 3 to AVDD 0 3 V Digital input or output to DGND 0 3 to IOVDD 0 3 V Maximum junction temperature 150 C ADS1...

Page 3: ... fCLK 27MHz 105 469 SPS Data rate fDATA High Resolution mode 52 734 SPS Low Power mode 52 734 SPS Low Speed mode 10 547 SPS Integral nonlinearity INL 4 Differential input VCM 2 5V 0 0003 0 0012 FSR 1 Offset error 0 25 2 mV Offset drift 0 8 μV C Gain error 0 1 0 5 FSR Gain drift 1 3 ppm C High Speed mode Shorted input 8 5 16 μV rms High Resolution mode Shorted input 5 5 12 μV rms Noise Low Power mo...

Page 4: ...Complete settling 76 fDATA s VOLTAGE REFERENCE INPUTS Negative reference input VREFN AGND 0 1 AGND 0 1 V 0 1 fCLK 27MHz 0 5 2 5 3 1 V Reference input voltage VREF 8 27 fCLK 32 768MHz 0 5 2 5 2 6 V VREF VREFP VREFN 32 768MHz fCLK 37MHz 0 5 2 048 2 1 V High Speed mode 1 3 kΩ High Resolution mode 1 3 kΩ ADS1274 Reference Input impedance Low Power mode 2 6 kΩ Low Speed mode 13 kΩ High Speed mode 0 65 ...

Page 5: ...mode 0 075 0 3 mA ADS1274 IOVDD current Low Power mode 0 075 0 3 mA Low Speed mode 0 02 0 15 mA High Speed mode 285 420 mW High Resolution mode 275 410 mW ADS1274 Power dissipation Low Power mode 135 210 mW Low Speed mode 30 55 mW ADS1278 High Speed mode 97 145 mA High Resolution mode 97 145 mA ADS1278 AVDD current Low Power mode 44 64 mA Low Speed mode 9 14 mA High Speed mode 23 30 mA High Resolu...

Page 6: ...S1274 ADS1278 SBAS367F JUNE 2007 REVISED FEBRUARY 2011 www ti com ADS1274 ADS1278 PIN ASSIGNMENTS PAP PACKAGE HTQFP 64 TOP VIEW 1 Boldface pin names indicate additional pins for the ADS1278 see Table 1 Table 1 ADS1274 ADS1278 PIN DESCRIPTIONS PIN NAME NO FUNCTION DESCRIPTION 6 43 54 AGND Analog ground Analog ground connect to DGND using a single plane 58 59 AINP1 3 Analog input AINP2 1 Analog inpu...

Page 7: ...ternally connected to active circuitry outputs are driven DOUT6 15 Digital output DOUT 4 1 Data output for channels 4 through 1 DOUT7 14 Digital output DOUT8 13 Digital output DRDY 29 Digital input output Frame Sync protocol frame clock input SPI protocol data ready output FSYNC DVDD 26 Digital power supply Digital core power supply FORMAT0 32 Digital input FORMAT 2 0 Selects Frame Sync SPI protoc...

Page 8: ...dge of DRDY 18 ns tSCLK 4 SCLK period 1 tCLK tSPW SCLK positive or negative pulse width 0 4 tCLK tDOHD 3 5 SCLK falling edge to new DOUT invalid hold time 10 ns 32 ns tDOPD 3 SCLK falling edge to new DOUT valid propagation delay 26 ns 6 tDIST New DIN valid to falling edge of SCLK setup time 6 ns tDIHD 5 Old DIN valid to falling edge of SCLK hold time 6 ns 1 fCLK 27MHz maximum 2 Depends on MODE 1 0...

Page 9: ...SCLK positive or negative pulse width 0 4 tCLK tDOHD 3 4 SCLK falling edge to old DOUT invalid hold time 10 ns 31 ns tDOPD 4 SCLK falling edge to new DOUT valid propagation delay 21 ns 5 25 ns 6 31 ns tMSBPD FSYNC rising edge to DOUT MSB valid propagation delay 21 ns 5 25 ns 6 tDIST New DIN valid to falling edge of SCLK setup time 6 ns tDIHD 3 Old DIN valid to falling edge of SCLK hold time 6 ns 1...

Page 10: ...Frequency Hz 0 20 40 60 80 100 120 140 160 Amplitude dB 10k 100k High Resolution Mode f 1kHz 0 5dBFS IN 32 768 Points 10 100 1k Frequency Hz 0 20 40 60 80 100 120 140 160 Amplitude dB 10k 100k High Resolution Mode f 1kHz 20dBFS IN 32 768 Points ADS1274 ADS1278 SBAS367F JUNE 2007 REVISED FEBRUARY 2011 www ti com TYPICAL CHARACTERISTICS At TA 25 C High Speed mode AVDD 5V DVDD 1 8V IOVDD 3 3V fCLK 27...

Page 11: ... 1 10 100 1k Frequency Hz 0 20 40 60 80 100 120 140 160 180 Amplitude dB 10k 100k Low Power Mode Shorted Input 262 144 Points 37 32 26 21 16 11 5 0 5 11 16 21 26 32 37 Output V m 25k 20k 15k 10k 5k 0 Number of Occurrences Low Power Mode Shorted Input 262 144 Points ADS1274 ADS1278 www ti com SBAS367F JUNE 2007 REVISED FEBRUARY 2011 TYPICAL CHARACTERISTICS continued At TA 25 C High Speed mode AVDD ...

Page 12: ...0 100 120 140 THD THD N dB 10k 100k High Speed Mode V 0 5dBFS IN THD N THD 120 100 80 60 40 Input Amplitude dBFS 0 20 40 60 80 100 120 140 THD THD N dB 20 0 High Speed Mode f 1kHz IN THD N THD ADS1274 ADS1278 SBAS367F JUNE 2007 REVISED FEBRUARY 2011 www ti com TYPICAL CHARACTERISTICS continued At TA 25 C High Speed mode AVDD 5V DVDD 1 8V IOVDD 3 3V fCLK 27MHz VREFP 2 5V and VREFN 0V unless otherwi...

Page 13: ...N THD N THD 120 100 80 60 40 Input Amplitude dBFS 0 20 40 60 80 100 120 140 THD THD N dB 20 0 Low Speed Mode THD N THD ADS1274 ADS1278 www ti com SBAS367F JUNE 2007 REVISED FEBRUARY 2011 TYPICAL CHARACTERISTICS continued At TA 25 C High Speed mode AVDD 5V DVDD 1 8V IOVDD 3 3V fCLK 27MHz VREFP 2 5V and VREFN 0V unless otherwise noted TOTAL HARMONIC DISTORTION TOTAL HARMONIC DISTORTION vs FREQUENCY ...

Page 14: ...h Resolution Modes ADS1278 Low Speed Mode ADS1278 Low Power Mode 1000 900 800 700 600 500 400 300 200 100 0 100 200 300 400 500 600 700 800 900 1000 Offset V m 40 35 30 25 20 15 10 5 0 Number of Occurrences High Speed Mode 25 Units 4000 3600 3200 2800 2400 2000 1600 1200 800 400 0 400 800 1200 1600 2000 2400 2800 3200 3600 4000 Gain Error ppm 90 80 70 60 50 40 30 20 10 0 Number of Occurrences High...

Page 15: ...0 60 80 100 Temperature C 1 36 1 34 1 32 1 30 1 28 1 26 1 24 1 22 Reference Input Impedance k W 13 6 13 4 13 2 13 0 12 8 12 6 12 4 12 2 Reference Input Impedance k W 120 125 High Speed and High Resolution Modes Low Speed Mode 50 100 150 200 250 300 350 400 450 500 550 600 650 700 Sampling Match Error ps 40 35 30 25 20 15 10 5 0 Number of Occurrences 30 units over 3 production lots inter channel co...

Page 16: ... 5 1 0 0 5 0 0 5 1 0 1 5 2 0 T 40 C T 25 C T 125 C T 105 C 0 V V REF 14 12 10 8 6 4 2 0 Linearity ppm 100 104 108 112 116 120 124 128 THD dB 3 5 THD 0 5 1 0 1 5 2 0 2 5 3 0 Linearity THD f 1kHz V 0 5dBFS IN IN See for Electrical Characteristics V Operating Range REF ADS1274 ADS1278 SBAS367F JUNE 2007 REVISED FEBRUARY 2011 www ti com TYPICAL CHARACTERISTICS continued At TA 25 C High Speed mode AVDD...

Page 17: ...se Shorted Input Noise THD 10 100 1k Input Frequency Hz 0 20 40 60 80 100 120 Common Mode Rejection dB 10k 100k 1M 10 100 1k Power Supply Modulation Frequency Hz 0 20 40 60 80 100 120 Power Supply Rejection dB 10k 100k 1M AVDD IOVDD DVDD ADS1274 ADS1278 www ti com SBAS367F JUNE 2007 REVISED FEBRUARY 2011 TYPICAL CHARACTERISTICS continued At TA 25 C High Speed mode AVDD 5V DVDD 1 8V IOVDD 3 3V fCLK...

Page 18: ...0 100 80 60 40 20 0 AVDD Current mA 120 125 High Speed and High Resolution Modes Low Power Mode Low Speed Mode 40 20 0 20 40 60 80 100 Temperature C 30 25 20 15 10 5 0 DVDD Current mA 120 125 High Resolution Mode High Speed Mode Low Power Mode Low Speed Mode ADS1274 ADS1278 SBAS367F JUNE 2007 REVISED FEBRUARY 2011 www ti com TYPICAL CHARACTERISTICS continued At TA 25 C High Speed mode AVDD 5V DVDD...

Page 19: ...de High Speed Mode Low Power Mode Low Speed Mode ADS1274 ADS1278 www ti com SBAS367F JUNE 2007 REVISED FEBRUARY 2011 TYPICAL CHARACTERISTICS continued At TA 25 C High Speed mode AVDD 5V DVDD 1 8V IOVDD 3 3V fCLK 27MHz VREFP 2 5V and VREFN 0V unless otherwise noted ADS1278 IOVDD CURRENT ADS1278 POWER DISSIPATION vs TEMPERATURE vs TEMPERATURE Figure 55 Figure 56 2007 2011 Texas Instruments Incorpora...

Page 20: ... 10 5kSPS The digital filters can be bypassed expandability The converters are comprised of four enabling direct access to the modulator output ADS1274 or eight ADS1278 advanced 6th order The ADS1274 78 is configured by simply setting the chopper stabilized delta sigma modulators followed appropriate I O pins there are no registers to by low ripple linear phase FIR filters The modulators program D...

Page 21: ... clock distribution devices can be used to reduce the modulator at a high rate typically 64x higher than the sampling match error between devices final output data rate The quantization noise of the modulator is moved to a higher frequency range FREQUENCY RESPONSE where the internal digital filter removes it Oversampling results in very low levels of noise The digital filter sets the overall frequ...

Page 22: ...fMOD as shown in Figure 61 Figure 60 Transition Band Response for High Speed Low Power and Low Speed Modes Figure 58 Frequency Response for High Speed Low Power and Low Speed Modes Figure 61 Frequency Response Out to fMOD for High Speed Low Power and Low Speed Modes These image frequencies if present in the signal and not externally filtered will fold back or alias into the passband causing errors...

Page 23: ... passband to stop band is shown in Figure 64 The overall frequency response repeats at multiples of the modulator frequency fMOD 128 fDATA as shown in Figure 65 The stop band of the ADS1274 78 provides 100dB attenuation of frequencies that begin just beyond the passband and continue out to fMOD Placing an antialiasing low pass filter in front of the ADS1274 78 inputs is recommended to limit possib...

Page 24: ...nversion periods for High Resolution mode which produces the most positive digital output code of 7FFFFFh Likewise the most negative measurable differential input is VREF which produces the most negative digital output code of 800000h For optimum performance the inputs of the ADS1274 78 are intended to be driven differentially For single ended applications one of the inputs AINP or AINN can be dri...

Page 25: ...e is common to all channels The reference inputs use a structure similar to that of the analog inputs with the equivalent circuitry on the reference inputs shown in Figure 70 As with the analog inputs the load presented by the switched capacitor can be modeled with an effective impedance as shown in Figure 71 However the reference input impedance depends on the number of active enabled channels in...

Page 26: ...tting of the Low Speed The modes offer optimization of speed CLKDIV input For High Speed mode the maximum resolution and power Mode selection is determined CLK input frequency is 37MHz For High Resolution by the status of the digital input MODE 1 0 pins as mode the maximum CLK input frequency is 27MHz shown in Table 9 The ADS1274 78 continually In High Speed mode operating conditions are monitors ...

Page 27: ...rned such as the changing of an external multiplexer on high DRDY stays high while the digital filter is the analog inputs or by a reference timing pulse settling Once valid data are ready for retrieval DRDY goes low Because the ADS1274 78 converters operate in parallel from the same master clock and use the In the Frame Sync format DOUT goes low as soon same SYNC input control they are always in ...

Page 28: ...ersions 1 fDATA Figure 74 Synchronization Timing Frame Sync Protocol Table 12 Frame Sync Protocol SYMBOL DESCRIPTION MIN TYP MAX UNITS tCSHD CLK to SYNC hold time 10 ns tSCSU SYNC to CLK setup time 5 ns tSYN Synchronize pulse width 1 CLK periods tNDR Time for new data to be ready 1 127 128 Conversions 1 fDATA 1 If SYNC is asynchronous to the FSYNC clock then tNDR varies from 127 to 128 conversions...

Page 29: ...data format the data are always forced to As shown in Figure 75 and Table 13 a maximum of zero When powering up a channel in 130 conversion cycles must elapse for SPI interface dynamic position TDM data format mode the channel and 129 conversion cycles must elapse for data remain packed until the data are ready at which Frame Sync before reading data after exiting time the data frame is expanded t...

Page 30: ...74 78 using the serial interface Two protocols are available SPI and Frame Sync The same pins are used for both interfaces SCLK DRDY FSYNC DOUT 4 1 DOUT 8 1 for ADS1278 and DIN The FORMAT 2 0 pins select the desired interface Figure 76 DRDY Timing with No Readback protocol SPI SERIAL INTERFACE DOUT The SPI compatible format is a read only interface The conversion data are output on DOUT 4 1 8 1 Da...

Page 31: ...DES from accidentally shifting the data When using For both SPI and Frame Sync interface protocols the Frame Sync format SCLK must run continuously If it data are shifted out either through individual channel is shut down the data readback will be corrupted DOUT pins in a parallel data format Discrete mode The number of SCLKs within a frame period FSYNC or the data for all channels are shifted out...

Page 32: ...hannel is powered one position in the data stream to fill the vacated data down the data are forced to zero but occupy the slot Figure 79 shows the data stream with channel 1 same position within the data stream Figure 78 and channel 3 powered down shows the data stream with channel 1 and channel 3 powered down Discrete Data Output Mode In Discrete data output mode the channel data are shifted out...

Page 33: ...interface protocol is SPI or Frame Sync The frequency of fSCLK must be high enough to it is recommended to synchronize all devices by tying completely shift the data out from all channels within the SYNC inputs together When synchronized in SPI one fDATA period Table 15 lists the maximum number protocol it is only necessary to monitor the DRDY of daisy chained channels when fSCLK fCLK output of on...

Page 34: ...ata Devices 1 and 2 Serial Data Devices 3 and 4 SCLK ADS1274 78 CLK CLK CLK DIN DIN U4 U3 U2 U1 ADS1274 ADS1278 SBAS367F JUNE 2007 REVISED FEBRUARY 2011 www ti com NOTE The number of chained devices is limited by the SCLK rate and device mode Figure 81 Daisy Chaining of Two Devices SPI Protocol FORMAT 2 0 000 or 001 Figure 82 Daisy Chain Data Format of Figure 81 ADS1278 shown NOTE The number of ch...

Page 35: ... becomes Figure 84 shows the start up sequence of the the modulator clock output The DRDY FSYNC pin ADS1274 78 At power on bring up the DVDD supply becomes an unused output and can be ignored The first followed by IOVDD and then AVDD Check the normal operation of the Frame Sync and SPI power supply sequence for proper order including interfaces is disabled and the functionality of SCLK the ramp ra...

Page 36: ...ge output equal to AVDD 2 The intended use of this output is to set the PIN TEST USING TEST 1 0 INPUTS output common mode level of the analog input The test mode feature of the ADS1274 and ADS1278 drivers The drive capability of the output is limited allows continuity testing of the digital I O pins In this therefore the output should only be used to drive mode the normal functions of the digital ...

Page 37: ...ching power supply source directly across the analog input pins AINP and is used the voltage ripple should be low less AINN A low k dielectric such as COG or film than 2mV and the switching frequency outside type should be used to maintain low THD the passband of the converter Capacitors from each analog input to ground can 2 Ground Plane A single ground plane connecting be used They should be no ...

Page 38: ...U1 U2 CLKR Q Q 0 3 3V MODE0 IN1 IN4 8 1 F m 5V See Note 6 ADS1274 ADS1278 SBAS367F JUNE 2007 REVISED FEBRUARY 2011 www ti com 1 External Schottky clamp diodes or series resistors may be needed to prevent overvoltage on the inputs Place the THS4521 drivers close to the ADS1278 inputs 2 Indicates ceramic capacitors 3 Indicates COG ceramic capacitors 4 Optional For pin test mode 5 U1 SN74LVC1G04 U2 S...

Page 39: ...D FEBRUARY 2011 1 Bypass with 10μF and 0 1μF capacitors 1 Bypass with 10μF and 0 1μF capacitors 2 2 7nF for Low Power mode 15nF for Low Speed mode 2 10nF for Low Power mode 56nF for Low Speed mode 3 Alternate driver OPA1632 using 12V supplies 3 Alternate driver OPA1632 using 12V supplies Figure 89 Basic Differential Input Signal Figure 90 Basic Single Ended Input Signal Interface Interface 2007 20...

Page 40: ...me die pad using thermally and vias connected to the PCB ground plane the conductive epoxy The package is molded so that the board designer can now implement power packaging leadframe die pad is exposed at a surface of the without additional thermal hardware for example package This design provides an extremely low external heatsinks or the need for specialized thermal resistance to the path betwe...

Page 41: ...s publishes the PowerPAD Figure 93 shows the required thermal pad etch Thermally Enhanced Package Application Report TI pattern for the HTQFP 64 package used for the literature number SLMA002 available for download ADS1274 Nine 13mil 0 33mm thermal vias plated at www ti com that provides a more detailed with 1 ounce of copper are placed within the thermal discussion of PowerPAD design and layout p...

Page 42: ...6mils 8mm 316mils 8mm Thermal Pad Package Outline ADS1274 ADS1278 SBAS367F JUNE 2007 REVISED FEBRUARY 2011 www ti com Figure 93 Thermal Pad Etch and Via Pattern for the HTQFP 64 Package 42 Submit Documentation Feedback 2007 2011 Texas Instruments Incorporated Product Folder Link s ADS1274 ADS1278 ...

Page 43: ...sion F Page Deleted selective disclosure statement from document 1 Changes from Revision D July 2009 to Revision E Page Added supplemental timing requirements tDOPD to SPI Format Timing Specification table 8 Added supplemental timing requirements tDOPD and tMSBPD to Frame Sync Format Timing Specification table 9 2007 2011 Texas Instruments Incorporated Submit Documentation Feedback 43 Product Fold...

Page 44: ...production Samples may or may not be available OBSOLETE TI has discontinued the production of the device 2 RoHS TI defines RoHS to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances including the requirement that RoHS substance do not exceed 0 1 by weight in homogeneous materials Where designed to be soldered at high temperatures RoHS pr...

Page 45: ...mation from third parties TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals TI and TI suppliers consider certain information to be proprietary and thus CAS numbers and other limited information may not be available for release In no event shal...

Page 46: ...Pin1 Quadrant ADS1274IPAPR HTQFP PAP 64 1000 330 0 24 4 13 0 13 0 1 5 16 0 24 0 Q2 ADS1274IPAPT HTQFP PAP 64 250 180 0 24 4 13 0 13 0 1 5 16 0 24 0 Q2 ADS1278IPAPR HTQFP PAP 64 1000 330 0 24 4 13 0 13 0 1 5 16 0 24 0 Q2 ADS1278IPAPT HTQFP PAP 64 250 180 0 24 4 13 0 13 0 1 5 16 0 24 0 Q2 PACKAGE MATERIALS INFORMATION www ti com 14 Feb 2019 Pack Materials Page 1 ...

Page 47: ... Width mm Height mm ADS1274IPAPR HTQFP PAP 64 1000 350 0 350 0 43 0 ADS1274IPAPT HTQFP PAP 64 250 213 0 191 0 55 0 ADS1278IPAPR HTQFP PAP 64 1000 350 0 350 0 43 0 ADS1278IPAPT HTQFP PAP 64 250 213 0 191 0 55 0 PACKAGE MATERIALS INFORMATION www ti com 14 Feb 2019 Pack Materials Page 2 ...

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Page 51: ...se resources are subject to change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and display of these resources is prohibited No license is granted to any other TI intellectual property right or to any third party intellectual property right TI disclaims responsibility for...

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