Texas Instruments ADS1271EVM, User Manual, Page: 10 / 24

ADS1271EVM Hardware Details
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5.2.2.1 Buffer Amplifiers
The buffer amplifiers on this EVM are OPA1632s (U5, U6). These amplifiers are optimized for ac
performance and are configured as fully-differential unity gain buffers. They require ±15V supplies, which
are provided from J3 pins 1 and 2.
The OPA1632 requires a common-mode voltage, which is provided on this EVM by U2 and U3. Some
users may not wish to use the buffer amplifier section and provide the ±15V supplies. If the ±15V supplies
are not connected, then having a voltage on the V
OCM
pins of the amplifiers would exceed their maximum
ratings. Thus, U2 and U3 provide a separate 2.5V reference for the buffer amplifier section rather than
using the same reference as the ADS1271, which would always be powered. For this reason, U2 and U3
power is provided through a separate regulator, U11.
5.3 Digital Interface, J2
The ADS1271EVM is designed to easily interface with multiple control platforms. Samtec part numbers
SSW-110-22-F-D-VS-K and TSM-110-01-T-DV-P provide a convenient 10-pin, dual-row, header/socket
combination at J2. This header/socket provides access to the digital control and serial data pins of the
ADS1271.
Because the ADS1271 devices are capable of daisy-chaining, this EVM has been designed to permit
stacking; up to four EVMs can be stacked, allowing for eight devices to be placed in a signal chain. To
accommodate stacking of EVMs, J2 has some different connections on the top and the bottom side of the
board. Differences between top and bottom connectors are highlighted in
Table 10 .
Table 10. Digital Interface Pinout (J2)
Pin Number Signal Description
J2.1 SYNC Synchronization Control
J2.2 MODE0 0 = High-Speed Mode
1 = Low-Power Mode
(In either case, only if Mode1=0)
J2.3 CLKX CLKXMODE = 1: master clock output
CLKXMODE = 0: no connection
J2.4 DGND Digital ground
J2.5 SCLK Serial Clock
J2.6 MODE1 0 = Mode determined by MODE0
1 = High-Resolution Mode
J2.7 Unused.
J2.8 FSDIR Indicates FSR direction:
0 = Output (DRDY in SPI™ mode)
1 = Input (FSYNC mode)
J2.9 Top: FSOUT FSOUT: in FSYNC mode, copy of FSR; in SPI mode, not connected
Bottom: FSR FSR: in FSYNC mode, frame-sync input; in SPI mode, DRDY output from U8
J2.10 DGND Digital ground
J2.11 Unused
J2.12 CLKRMODE 0 = Use CLKR for SPI Clock
1 = Use ADC Clock for SPI clock
J2.13 Top: DIN Top: Serial data input
Bottom: DOUT Bottom: Serial data output
J2.14 CLKXMODE 0 = CLKX is High Z
1 = CLKX outputs ADC master clock
J2.15 Unused
J2.16 SCL I
2
C™ bus serial clock
J2.17 EXTCLK External ADC clock input
J2.18 DGND Digital ground
J2.19 OBCLKSEL Onboard Clock Select:
High to select onboard clock instead of external clock.
10 ADS1271EVM and ADS1271EVM-PDK User's Guide SBAU107C – November 2004 – Revised November 2014
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