Texas Instruments ADS1174EVM, User Manual, Page: 4 / 48

2 Analog Interface
3 Digital Interface
3.1 Serial Data Interface
Analog Interface
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For maximum flexibility, the ADS1274EVM is designed for easy interfacing to multiple analog sources.
Samtec part numbers SSW-110-22-F-D-VS-K and TSM-110-01-T-DV-P provide a convenient 10-pin,
dual-row, header/socket combination at J9. This header/socket provides access to the analog input pins of
the ADS1274. Consult Samtec at
http://www.samtec.com or call 1-800-SAMTEC-9 for a variety of mating
connector options. These signals can also be connected to the terminal block J7.
Most of the pins on J7 and J9 are directly connected, with no filtering or protection. Use appropriate
caution when handling these pins.
Table 1 summarizes the pinouts for analog interfaces J9 and J7.
Table 1. J9/J7:Analog Interface Pinout
Pin Number Signal Description
J9.1, J7-2 A1N AINN1, ADS1274
J9.2, J7-3 A1P AINP1, ADS1274
J9.3, J7-4 A2N AINN2, ADS1274
J9.4, J7-5 A2P AINP2, ADS1274
J9.5, J7-6 A3N AINN3, ADS1274
J9.6, J7-7 A3P AINP3, ADS1274
J9.7, J7-8 A4N AINN4, ADS1274
J9.8, J7-9 A4P AINP4, ADS1274
J9.18 EXTREFN External Reference source input
(– side of differential input)
J9.20 EXTREFP External Reference source input
(+ side of differential input)
J9.10-16 (even) Unused
J9.15 Unused
J9.9-19 (odd), J7-1 AGND Analog ground connections (except J1.15)
The ADS1274EVM is designed to easily interface with multiple control platforms. Samtec part numbers
SSW-110-22-F-D-VS-K and TSM-110-01-T-DV-P provide a convenient 10-pin, dual-row, header/socket
combination at J5. This header/socket provides access to the digital control and serial data pins of the
ADC. Consult Samtec at
http://www.samtec.com or call 1-800-SAMTEC-9 for a variety of mating
connector options.
All logic levels on J5 are 3.3V CMOS, except for the I
2
C™ pins. These pins conform to 3.3V I
2
C rules.
Table 2 describes the J5 serial interface pins.
Table 2. J5: Serial Interface Pins
Pin No. Pin Name Signal Name I/O Type Pullup Function
J5.1 CNTL SYNC In High
J5.2 GPIO0 MODE0 In High
J5.3 CLKX SCLK In None ADS1274 SPI™
clock
J5.4 DGND DGND In/Out None Digital Ground
J5.5 CLKR CLKR Out None SCLK clock
J5.6 GPIO1 MODE1 In High
J5.7 FSX /DRDY/FSYNC In/Out Low
J5.8 GPIO2 FORMAT0 In High
4 ADS1174EVM, ADS1274EVM, ADS1174EVM-PDK, and ADS1274EVM-PDK SBAU134A – August 2008 – Revised May 2009
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