8 Test Pattern
It is often useful to utilize test patterns to help verify the correct reciept of digital data at the microcontroller or
FPGA. A ramp pattern can be enabled by following these steps:
• Click the yellow button "Analog Inputs and Clk"
• Next to "Test Pattern CHA", click the drop down menu, and select "RAMP CUSTOM". This can be done for
"Test Pattern CHB" as well.
• In the field next to "Custom Pattern",
– For 18 bit ramp mode (ADC3683EVM, ADC3682EVM), "1" must be entered in the "Custom Pattern" field.
• The digital ramp pattern is now enabled on the ADC. The output of the ADC is now an 18 bit, incrementing
ramp pattern.
Figure 8-1. ADC36xxEVM 18-bit Ramp Pattern
• In HSDC Pro, the ramp pattern can now be seen when data is captured. These same steps apply to any data
output mode (Bypass, Real Decimation and Complex Decimation).
– It may be necessary to increase the capture sample size to 524k to capture the entire ramp pattern in 18
bit mode.
– In HSDC Pro, click "Data Capture Options" -> "Capture Option", and enter "524288" in the "# of samples
(per channel)" field.
Test Pattern
SBAU360 – DECEMBER 2020
ADC368xEVM Evaluation Module
27
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