Texas Instruments ADC08L060EVM, User Manual, Page: 11 / 16

11 SLAU712 – February 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Jumper and Connector Descriptions
Appendix A
SLAU712 – February 2017
Jumper and Connector Descriptions
A.1 Jumper Descriptions
The EVM jumpers are shown in Table 4 as well as the default settings for the jumpers. Use this table to
reset the EVM in the default configuration, in case of issues.
Table 4. Jumper Descriptions and Default Settings
Jumper Description Default Setting
JP1 INH function for onboard sample clock (active, by default) OPEN
JP2 Selects either onboard or external sample clock (default is onboard) Shunt pins 1-2
JP3 Option to bypass clock buffer (not bypassed, by default) OPEN
JP4 Enable outputs from clock buffer (active high) Shunt pins 1-2
JP5 Option to bypass clock buffer (not bypassed, by default) Shunt pins 2-3
JP6 Powerdown mode for ADC08L060 (default not in powerdown mode) Shunt pins 2-3
JP7 Provides power to onboard clock (powered, by default) Shunt pins 1-2
JP8 Top reference voltage option (supplied by LM8272, by default) Shunt pins 1-2
JP9 Bottom reference voltage option (supplied by LM8272, by default) Shunt pins 1-2
A.2 Connector Descriptions
The EVM connectors and their function are described in Table 5 .
Table 5. Connector Descriptions
Connector Description
J1 CMOS pin header connector
J2 Clock output for ADC sampling and FPGA
J3 External ADC sample clock input
J4 5-V DC banana jack connector
J5 GND banana jack connector
J6 Single-ended SMA analog input