TCP460 User Manual Issue 1.1
Page 9 of 32
3.1 Secondary PCI Bus Overview
The following chart gives information about the device numbers of the octal PCI UARTs and how their
interrupts are wired to the Primary PCI Bus:
Secondary PCI Bus
Device Number
Primary PCI Bus
Interrupt Line
Octal UART1
4 (AD20 used as IDSEL)
INTA#
Octal UART2
5 (AD21 used as IDSEL)
INTB#
Figure 3-3 : Secondary PCI Bus Overview
3.2 PCI2050B PCI-to-PCI Bridge General Info
Vendor ID: 0x104C (Texas Instruments)
Device ID: 0xAC28 (PCI2050b)
The general purpose I/O interface is not used. GPIO pins are pulled up.
Only secondary clock outputs 0-1 and 9 are used to clock secondary devices. The host software may
disable clock outputs 2-8 through the secondary clock control register located at PCI offset 0x68 to
save power.
For detailed description of the PCI2050B PCI-to-PCI Bridge refer to the PCI2050B datasheet, which is
available on the Texas Instruments website (
www.ti.com
). The PCI2050B data sheet is also part of the
TCP460-ED Engineering Documentation.
