UM_8023C_027
73S8023C Demo Board User Manual
Rev. 1.2
13
5 73S8023C Demo Board Schematics, PCB Layouts and Bill of Materials
5.1 Schematic
R8
Ru
Signal Names refer
to 73S1121F
evaluation board
SIO
JP1
1
2
3
USR4
5V
Connectors are positioned to allow
multiple 8023C boards (stackin) to a
73S1121F evaluation board. Also used
for connectiong external signals when
usedas a stand alone board
USR3
USR2
J5
Smart Card Connector
1
2
3
4
5
6
7
8
9
1
0
VC
C
R
ST
C
LK
C4
GN
D
VPP
I/
O
C8
SW
-1
SW
-2
J4
TSM_110_01_L_SV
1
2
3
4
5
6
7
8
9
10
JP2
1
2
3
Resistors are
not populated
3.3V
C9
CARD DETECT
POLARITY SELECT
R1
CLKDIV2
5V
5V
JP4
HEADER LOCK 3
1
2
3
TP1
1
2
SCLK
+5V
SCLK
DO NOT
POPULATE
TP2
GND
R10
Ru
VDD
GND
J3
SSM_110_L_SV
1
2
3
4
5
6
7
8
9
10
10uH
R5
USR1
TP3
1
2
VDD
SELECT
R12
Rd
R13
Rd
SC8
RST
C12
27pF
+
C1
10uF
VCC
Resistors are
not populated
C11
3.3uF
VDD
TP4
1
2
VDDF_ADJ
XTALIN
SELECT
Keep CLK trace
away from RST
and I/O trace
Resistors are
not populated
R4
0
+3.3V
J6
SIM/SAM Connector
1
2
3
4
5
6
7
8
C1
C2
C3
C5
C6
C7
SW
1
SW
2
TEST
MUST SELECT 3.3V
Signal Names refer
to 73S1121F
evaluation board
R2
0
SCLK
S_C4
U2
73S8023C
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
17
18
19
20
21
22
23
24
2
5
2
6
2
7
2
8
2
9
3
0
3
1
3
2
GND
LIN
VPC
NC
PRDWN
PRES
PRES
CS
I/
O
AU
X2
AU
X1
GN
D
C
LK
R
ST
VC
C
C
L
KSEL
VDDF_ADJ
CMDVCC
RSTIN
VDD
GND
OFF
XTALIN
XTALOUT
ST
R
OBE
I/
O
UC
AU
X1U
C
AU
X2U
C
CL
K
DI
V
1
CL
K
DI
V
2
5
V
/3V
C
L
KOU
T
RSTIN
3.3V
USR5
Y 1
12.000MHz
1
4
+
C10
10uF
CLK
R9
Ru
C2
0.1uF
TP2
1
2
INT2
USR7
JP9
CLKOUT
1
2
VDD
5.0V
CLKDIV1
C13
27pF
3.3V
TP3 to TP8 to be placed
very close to the pads
of J5
5V3VB
SIO
VDD
5.0V
TP7
1
2
I/O
Card detection
switches are
nornally open
MUST SELECT 3.3V
C4
3.3V
JP6
1
2
3
C5
22pF
PR ES
USR6
R6
Jumper must
select VDD
GND
C8
0.1uF
R11
Rd
VPC
SELECT
OFFB
J1
SSM_110_L_SV
1
2
3
4
5
6
7
8
9
10
JP10
STROBE
1
2
Jumper must
select PRES
VDD
VDD
TP8
1
2
CMDVCCB
PRES
GND
TP6
1
2
SC4
3.3V
PGND
TP5
1
2
5.0V
GND
PRDWN
GND
C8
S_C8
C4
22pF
R14
+5V
R3
JP8
CS
1
2
3
JP7
CLKSEL
1
2
3
L1
GND
+
C3
10uF
J2
TSM_110_01_L_SV
1
2
3
4
5
6
7
8
9
10
XTAL
VDD
USR0
JP5
1
2
3
JP3
1
2
3
R7
0
Figure 5: 73S8023C Demo Board Electrical Schematic
