UG_1215F_039
73S1215F Evaluation Board User Guide
Rev. 1.8
33
4.6.5 Smart Card Interface
The smart card interface on the 73S1215F requires few external components for proper operation.
shows the recommended smart card interface connections.
•
The RST and CLK signals should have 27 pF capacitors at the smart card connector.
•
It is recommended that a 0
Ω
resistor be added in series with the CLK signal. If necessary, in noisy
environments, this resistor can be replaced with a small resistor to create a RC filter on the CLK
signal to reduce CLK noise. This filter is used to soften the clock edges and provide a cleaner clock
for those environments where this could be problematic.
•
The VCC output must have a 1.0
µ
F capacitor at the smart card connector for proper operation.
•
The VPC input is the power supply input for the smart card power. It is recommended that both a
10
µ
F and a 0.1
µ
F capacitor are connected to provide proper decoupling for this input.
•
The PRES input on the 73S1215F contains a very weak pull down resistor. As a result, an additional
external pull down resistor is recommended to prevent any system noise from triggering a false card
event. The same holds true for the
PRES
input, except a pull up resistor is utilized as the logic is
inverted from the PRES input.
The smart card interface layout is important. The following guidelines should be followed to provide the
optimum smart card interface operation:
•
Route auxiliary signals away from card interface signals
•
Keep CLK signal as short as possible and with few bends in the trace. Keep route of the CLK trace to
one layer (avoid vias to other plane). Keep CLK trace away from other traces especially RST and
VCC. Filtering of the CLK trace is allowed for noise purpose. Up to 30 pF to ground is allowed at the
CLK pin of the smart card connector. Also, the zero ohm series resistor, R7, can be replaced for
additional filtering (no more than 100
Ω
).
•
Keep VCC trace as short as possible. Make trace a minimum of 0.5 mm thick. Also, keep VCC away
from other traces especially RST and CLK.
•
Keep CLK trace away from VCC and RST traces. Up to 30 pF to ground is allowed for filtering
•
Keep 0.1
µ
F close to VDD pin of the device and directly take other end to ground
•
Keep 10
µ
F and 0.1
µ
F capacitors close to VPC pin of the device and directly take other end to
ground
•
Keep 1.0
µ
F close to VCC pin of the smart card connector and directly take other end to ground
1215
Figure 19: Smart Card Connections
http://www.datasheetcatalog.com/
