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Figure 4-5 Zoom-in Gesture
Note: execute the test.bat under Picture_Viewer\demo_batch will automatically download
the .sof and .elf file.
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This demonstration shows a digital camera reference design using the 5-Megapixel CMOS sensor
and 8-inch LCD modules on the VEEK-MT-C5SOC. The CMOS sensor module sends the raw
image data to FPGA on the Altera Cyclone® V SoC board, the FPGA on the board handles image
processing part and converts the data to RGB format to display on the LCD module. The I2C
Sensor Configuration module is used to configure the CMOS sensor module.
Figure 4-6
shows the
block diagram of the demonstration.
As soon as the configuration code is downloaded into the FPGA, the I2C Sensor Configuration
block will initial the CMOS sensor via I2C interface. The CMOS sensor is configured as follow:
••••
Row and Column Size: 800 * 480
••••
Exposure time: Adjustable
••••
Pix clock: MCLK*2 = 25*2 = 50MHz
••••
Readout modes: Binning
••••
Mirror mode: Line mirrored
According to the settings, we can calculate the CMOS sensor output frame rate is about 44.4 fps.
