20
Figure 4-4 Triple-Speed Ethernet Core Configuration
In the Mac Options section, the MDIO module is included that controls the PHY Management
Module associated with the MAC block shown in
. The host Clock divisor is to divide
the MAC control register interface clock to produce the MDC clock output on the MDIO interface.
The MAC control register interface clock frequency is 100 MHz and the desired MDC clock
frequency is 2.5 MHz, a host clock divisor of 40 should be used.
Summary of Contents for HSMC-NET
Page 1: ...HSMC NET Terasic HSMC NET Daughter Board User Manual ...
Page 9: ...8 Figure 2 3 The block diagram of the HSMC NET board ...
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