HAN Pilot Platform
Demonstration Manual
14
www.terasic.com
September 6, 2019
Nios II Program: DDR4_Test.elf
Demonstration Setup
Please follow below procedures to setup the demonstration.
1.
Make sure Quartus Prime and Nios II are installed on your PC.
2.
Make sure DDR4 SODIMM are installed on the FPGA board.
3.
Set MSEL[2:0] to 010.
4.
Power on the FPGA board.
5.
Use USB Cable to connect PC and the FPGA board and install USB Blaster II driver if
necessary.
6.
Execute the demo batch file “test.bat” under the folder “NIOS_DDR4\demo_batch”.
7.
After Nios II program is downloaded and executed successfully, a prompt message will be
displayed in nios2-terminal.
8.
Press Key0~Key1 of the FPGA board to start SDRAM verify process. Press Key0 for continued
test.
9.
The program will display progressing and result information, as shown in
Figure 2-13 Progress and Result Information for the DDR4 Demonstration
2.4
RTL DDR4 SDRAM Test
This demonstration performs a memory test function on the one DDR4 SO-DIMM (DDR4A) and
one DDR4 Component (DDR4B) on the HAN Pilot Platform. The memory size of DDR4
SO-DIMM is 4GB and DDR4 Component is 1GB.
Function Block Diagram