Terasic DE5-Net User Manual Download Page 33

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DE5-Net User Manual

www.terasic.com

June 20, 2018

Table 2-14

QDRII+ SRAM A Pin Assignments, Schematic Signal Names, and Functions

Schematic

Signal Name

Description

I/O Standard

Stratix V GX Pin

Number

QDRIIA_A0

Address bus[0]

1.8-V HSTL Class I

PIN_AU29

QDRIIA_A1

Address bus[1]

1.8-V HSTL Class I

PIN_BA28

QDRIIA_A2

Address bus[2]

1.8-V HSTL Class I

PIN_AP27

QDRIIA_A3

Address bus[3]

1.8-V HSTL Class I

PIN_AK27

QDRIIA_A4

Address bus[4]

1.8-V HSTL Class I

PIN_AN27

QDRIIA_A5

Address bus[5]

1.8-V HSTL Class I

PIN_AM28

QDRIIA_A6

Address bus[6]

1.8-V HSTL Class I

PIN_AV28

QDRIIA_A7

Address bus[7]

1.8-V HSTL Class I

PIN_AY27

QDRIIA_A8

Address bus[8]

1.8-V HSTL Class I

PIN_BC29

QDRIIA_A9

Address bus[9]

1.8-V HSTL Class I

PIN_AU28

QDRIIA_A10

Address bus[10]

1.8-V HSTL Class I

PIN_AW27

QDRIIA_A11

Address bus[11]

1.8-V HSTL Class I

PIN_AY28

QDRIIA_A12

Address bus[12]

1.8-V HSTL Class I

PIN_BD28

QDRIIA_A13

Address bus[13]

1.8-V HSTL Class I

PIN_AV29

QDRIIA_A14

Address bus[14]

1.8-V HSTL Class I

PIN_AW29

QDRIIA_A15

Address bus[15]

1.8-V HSTL Class I

PIN_BB29

QDRIIA_A16

Address bus[16]

1.8-V HSTL Class I

PIN_BD29

QDRIIA_A17

Address bus[17]

1.8-V HSTL Class I

PIN_AL27

QDRIIA_A18

Address bus[18]

1.8-V HSTL Class I

PIN_AR27

QDRIIA_A19

Address bus[19]

1.8-V HSTL Class I

PIN_AL28

QDRIIA_A20

Address bus[20]

1.8-V HSTL Class I

PIN_AR28

QDRIIA_D0

Write data bus[0]

1.8-V HSTL Class I

PIN_AH28

QDRIIA_D1

Write data bus[1]

1.8-V HSTL Class I

PIN_AH27

QDRIIA_D2

Write data bus[2]

1.8-V HSTL Class I

PIN_AH25

QDRIIA_D3

Write data bus[3]

1.8-V HSTL Class I

PIN_AJ28

QDRIIA_D4

Write data bus[4]

1.8-V HSTL Class I

PIN_AJ27

QDRIIA_D5

Write data bus[5]

1.8-V HSTL Class I

PIN_AJ26

QDRIIA_D6

Write data bus[6]

1.8-V HSTL Class I

PIN_AJ25

QDRIIA_D7

Write data bus[7]

1.8-V HSTL Class I

PIN_AL25

QDRIIA_D8

Write data bus[8]

1.8-V HSTL Class I

PIN_AH24

QDRIIA_D9

Write data bus[9]

1.8-V HSTL Class I

PIN_AN25

QDRIIA_D10

Write data bus[10]

1.8-V HSTL Class I

PIN_AM26

QDRIIA_D11

Write data bus[11]

1.8-V HSTL Class I

PIN_AM25

QDRIIA_D12

Write data bus[12]

1.8-V HSTL Class I

PIN_AL26

QDRIIA_D13

Write data bus[13]

1.8-V HSTL Class I

PIN_AK26

QDRIIA_D14

Write data bus[14]

1.8-V HSTL Class I

PIN_AU27

QDRIIA_D15

Write data bus[15]

1.8-V HSTL Class I

PIN_AU26

QDRIIA_D16

Write data bus[16]

1.8-V HSTL Class I

PIN_AV26

QDRIIA_D17

Write data bus[17]

1.8-V HSTL Class I

PIN_AW26

QDRIIA_Q0

Read Data bus[0]

1.8-V HSTL Class I

PIN_AK23

Summary of Contents for DE5-Net

Page 1: ...DE5 Net User Manual www terasic com June 20 2018 1...

Page 2: ...18 2 5 CLOCK CIRCUIT 19 2 6 RS 422 SERIAL PORT 21 2 7 FLASH MEMORY 22 2 8 DDR3 SO DIMM 25 2 9 QDRII SRAM 32 2 10 SPF PORTS 40 2 11 PCI EXPRESS 42 2 12 SATA 44 CHAPTER 3 SYSTEM BUILDER 48 3 1 INTRODUCT...

Page 3: ...3 SDRAM TEST 81 6 3 DDR3 SDRAM TEST BY NIOS II 83 CHAPTER 7 PCI EXPRESS REFERENCE DESIGN 87 7 1 PCI EXPRESS SYSTEM INFRASTRUCTURE 87 7 2 PC PCI EXPRESS SOFTWARE SDK 88 7 3 REFERENCE DESIGN FUNDAMENTAL...

Page 4: ...ix V GX FPGA features integrated transceivers that transfer at a maximum of 12 5 Gbps allowing the DE5 Net to be fully compliant with version 3 0 of the PCI Express standard as well as allowing an ult...

Page 5: ...iguration via MAX II CPLD and flash memory General user input output 10 LEDs 4 push buttons 4 slide switches 2 seven segment displays Clock System 50MHz Oscillator Programmable oscillators Si570 CDCM6...

Page 6: ...s edge connector power Mechanical Specification PCI Express full height and 3 4 length 1 1 3 3 B Bl lo oc ck k D Di ia ag gr ra am m 94H94HFigure 1 1 shows the block diagram of the DE5 Net board To pr...

Page 7: ...agram of the DE5 Net board Below is more detailed information regarding the blocks in Figure 1 1 Stratix V GX FPGA 5SGXEA7N2F45C2 622 000 logic elements LEs 50 Mbits embedded memory 48 transceivers 12...

Page 8: ...CPLD EPM2210 System Controller and Fast Passive Parallel FPP configuration Memory devices 32MB QDRII SRAM Up to 8GB DDR3 SO DIMM SDRAM 256MB FLASH General user I O 10 user controllable LEDs 4 user pu...

Page 9: ...18 9 Four SFP ports Four SFP connector 10 Gbps PCI Express x8 edge connector Support for PCIe Gen1 2 3 Edge connector for PC motherboard with x8 or x16 PCI Express slot Power Source PCI Express 6 pin...

Page 10: ...1 B Bo oa ar rd d O Ov ve er rv vi ie ew w Figure 2 1 is the top and bottom view of the DE5 Net development board It depicts the layout of the board and indicates the location of the connectors and k...

Page 11: ...the flash memory on power up For programming by on board USB Blaster II the following procedures show how to download a configuration bit stream into the Stratix V GX FPGA Make sure that power is pro...

Page 12: ...M2210 System Controller with the Embedded Blaster CPLD D17 Error Illuminates when the MAX II CPLD EPM2210 System Controller fails to configure the FPGA Driven by the MAX II CPLD EPM2210 System Control...

Page 13: ...l positions as shown in 9Figure 2 3 Figure 2 3 6 Position DIP switch for Configure Mode Select Flash Image for Configuration The Image Select DIP switch SW5 is provided to specify the image for config...

Page 14: ...A User Defined Push buttons The FPGA board includes four user defined push buttons that allow users to interact with the Stratix V GX device Each push button provides a high logic level or a low logic...

Page 15: ...the DOWN position or the UPPER position it provides a low logic level or a high logic level to the Stratix V GX FPGA respectively as shown in 0Figure 2 6 Figure 2 6 4 Slide switches Table 2 4 lists t...

Page 16: ...g a logic 0 on the I O port turns the LED ON Driving a logic 1 on the I O port turns the LED OFF 2 5 V PIN_AW37 D9 LED1 2 5 V PIN_AV37 D10 LED2 2 5 V PIN_BB36 D11 LED3 2 5 V PIN_BB39 D7 1 LED_BRACKET0...

Page 17: ...mes and Functions Board Reference Schematic Signal Name Description I O Standard Stratix V GX Pin Number HEX1 HEX1_D0 User Defined 7 Segment Display Driving logic 0 on the I O port turns the 7 segment...

Page 18: ...MBus which is connected to the Stratix V GX FPGA In addition the 7 bit POR slave address for this sensor is set to 0011000b An optional 3 pin 12V fan located on J15 of the FPGA board is intended to re...

Page 19: ...tor so each bank of FPGA I O bank 3 4 7 8 has two clock inputs The three programming oscillators are low jitter oscillators which are used to provide special and high quality clock signals for high sp...

Page 20: ...atix V GX Pin Number Application Y4 OSC_50_B3B 50 0 MHz 2 5 V PIN_AW35 OSC_50_B3D 1 8 V PIN_BC28 OSC_50_B4A 1 8 V PIN_AP10 OSC_50_B4D 1 8 V PIN_AY18 OSC_50_B7A 1 5 V PIN_M8 OSC_50_B7D 1 5 V PIN_J18 OS...

Page 21: ...0 U49 CLOCK_SCL 2 5 V PIN_AE15 I2C bus direct connected with Si570 CLOCK_SDA 2 5 V PIN_AE16 CDCM61001 U53 PLL_SCL 2 5 V PIN_AF32 I2C bus connected with MAX II CPLD PLL_SDA 2 5 V PIN_AG32 CDCM61004 U28...

Page 22: ...driver outputs into a high impedance state 2 5 V PIN_AG14 RS422_DIN Receiver Output The data is send to FPGA PIN_AE18 RS422_DOUT Driver Input The data is sent from FPGA PIN_AE17 RS422_RE_n Receiver En...

Page 23: ...n the Flash Max and Stratix V GX FPGA Table 2 11 lists the flash pin assignments signal names and functions Table 2 11 Flash Memory Pin Assignments Schematic Signal Names and Functions Schematic Signa...

Page 24: ...PIN_AG26 FSM_D1 Data bus 2 5 V PIN_AD33 FSM_D2 Data bus 2 5 V PIN_AE34 FSM_D3 Data bus 2 5 V PIN_AF31 FSM_D4 Data bus 2 5 V PIN_AG28 FSM_D5 Data bus 2 5 V PIN_AG30 FSM_D6 Data bus 2 5 V PIN_AF29 FSM_D...

Page 25: ...N_AY30 FLASH_WE_n Write enable 2 5 V PIN_AR31 FLASH_ADV_n Address valid 2 5 V PIN_AK29 FLASH_RDY_BSY_n 0 Ready of flash 0 2 5 V PIN_BA29 FLASH_RDY_BSY_n 1 Ready of flash 1 2 5 V PIN_BB32 2 2 8 8 D DD...

Page 26: ...es and Functions Schematic Signal Name Description I O Standard Stratix V GX Pin Number DDR3A_DQ0 Data 0 SSTL 15 Class I PIN_A35 DDR3A_DQ1 Data 1 SSTL 15 Class I PIN_A34 DDR3A_DQ2 Data 2 SSTL 15 Class...

Page 27: ...15 Class I PIN_R34 DDR3A_DQ29 Data 29 SSTL 15 Class I PIN_T34 DDR3A_DQ30 Data 30 SSTL 15 Class I PIN_W34 DDR3A_DQ31 Data 31 SSTL 15 Class I PIN_V35 DDR3A_DQ32 Data 32 SSTL 15 Class I PIN_P33 DDR3A_DQ3...

Page 28: ...IN_T35 DDR3A_DQS4 Data Strobe p 4 Differential 1 5 V SSTL Class I PIN_T33 DDR3A_DQS_n4 Data Strobe n 4 Differential 1 5 V SSTL Class I PIN_T32 DDR3A_DQS5 Data Strobe p 5 Differential 1 5 V SSTL Class...

Page 29: ...ential 1 5 V SSTL Class I PIN_H37 DDR3A_CKE0 Clock Enable pin 0 SSTL 15 Class I PIN_E36 DDR3A_CKE1 Clock Enable pin 1 SSTL 15 Class I PIN_B35 DDR3A_ODT0 On Die Termination 0 SSTL 15 Class I PIN_V36 DD...

Page 30: ...Class I PIN_J10 DDR3B_DQ27 Data 27 SSTL 15 Class I PIN_H12 DDR3B_DQ28 Data 28 SSTL 15 Class I PIN_N11 DDR3B_DQ29 Data 29 SSTL 15 Class I PIN_M11 DDR3B_DQ30 Data 30 SSTL 15 Class I PIN_H10 DDR3B_DQ31...

Page 31: ...5 V SSTL Class I PIN_K11 DDR3B_DQS_n3 Data Strobe n 3 Differential 1 5 V SSTL Class I PIN_L11 DDR3B_DQS4 Data Strobe p 4 Differential 1 5 V SSTL Class I PIN_U9 DDR3B_DQS_n4 Data Strobe n 4 Differentia...

Page 32: ...7 DDR3B_CK_n1 Clock n1 Differential 1 5 V SSTL Class I PIN_D17 DDR3B_CKE0 Clock Enable pin 0 SSTL 15 Class I PIN_P17 DDR3B_CKE1 Clock Enable pin 1 SSTL 15 Class I PIN_V18 DDR3B_ODT0 On Die Termination...

Page 33: ...I PIN_BD29 QDRIIA_A17 Address bus 17 1 8 V HSTL Class I PIN_AL27 QDRIIA_A18 Address bus 18 1 8 V HSTL Class I PIN_AR27 QDRIIA_A19 Address bus 19 1 8 V HSTL Class I PIN_AL28 QDRIIA_A20 Address bus 20 1...

Page 34: ...lass I PIN_AL24 QDRIIA_BWS_n0 Byte Write select 0 1 8 V HSTL Class I PIN_AJ24 QDRIIA_BWS_n1 Byte Write select 1 1 8 V HSTL Class I PIN_AT27 QDRIIA_K_P Clock P Differential 1 8 V HSTL Class I PIN_AP25...

Page 35: ...5 1 8 V HSTL Class I PIN_AU22 QDRIIB_D6 Write data bus 6 1 8 V HSTL Class I PIN_BA21 QDRIIB_D7 Write data bus 7 1 8 V HSTL Class I PIN_AY21 QDRIIB_D8 Write data bus 8 1 8 V HSTL Class I PIN_AW21 QDRII...

Page 36: ...PIN_AH18 QDRIIB_QVLD Valid Output Indicator 1 8 V HSTL Class I PIN_AJ16 Table 2 16 QDRII SRAM C Pin Assignments Schematic Signal Names and Functions Schematic Signal Name Description I O Standard Stra...

Page 37: ...PIN_AV11 QDRIIC_D17 Write data bus 17 1 8 V HSTL Class I PIN_AT12 QDRIIC_Q0 Read Data bus 0 1 8 V HSTL Class I PIN_BA12 QDRIIC_Q1 Read Data bus 1 1 8 V HSTL Class I PIN_AF14 QDRIIC_Q2 Read Data bus 2...

Page 38: ...V HSTL Class I PIN_U26 QDRIID_A7 Address bus 7 1 8 V HSTL Class I PIN_T26 QDRIID_A8 Address bus 8 1 8 V HSTL Class I PIN_T27 QDRIID_A9 Address bus 9 1 8 V HSTL Class I PIN_V27 QDRIID_A10 Address bus 1...

Page 39: ...s 6 1 8 V HSTL Class I PIN_A29 QDRIID_Q7 Read Data bus 7 1 8 V HSTL Class I PIN_A28 QDRIID_Q8 Read Data bus 8 1 8 V HSTL Class I PIN_B28 QDRIID_Q9 Read Data bus 9 1 8 V HSTL Class I PIN_G28 QDRIID_Q10...

Page 40: ...hem to optical signals The board includes cage assemblies for the SFP connectors 1Figure 2 14 shows the connections between the SFP and Stratix V GX FPGA Figure 2 14 Connection between the SFP and Str...

Page 41: ...ndicator 2 5V PIN_R22 SFPB_MOD0_PRSNT_nModule present 2 5V PIN_K22 SFPB_MOD1_SCL Serial 2 wire clock 2 5V PIN_K21 SFPB_MOD2_SDA Serial 2 wire data 2 5V PIN_K20 SFPB_RATESEL0 Rate select 0 2 5V PIN_R21...

Page 42: ...a Stratix V GX device it is able to provide a fully integrated PCI Express compliant solution for multi lane x1 x4 and x8 applications With the PCI Express hard IP block incorporated in the Stratix V...

Page 43: ...s 1 4 V PCML PIN_AV40 PCIE_TX_p2 Add in card transmit bus 1 4 V PCML PIN_AT39 PCIE_TX_n2 Add in card transmit bus 1 4 V PCML PIN_AT40 PCIE_TX_p3 Add in card transmit bus 1 4 V PCML PIN_AU41 PCIE_TX_n3...

Page 44: ...ce clock HCSL PIN_AK39 PCIE_PERST_n Reset 2 5 V PIN_AU33 PCIE_SMBCLK SMB clock 2 5 V PIN_BD34 PCIE_SMBDAT SMB data 2 5 V PIN_AT33 PCIE_WAKE_n Wake signal 2 5 V PIN_BD35 PCIE_PRSNT1n Hot plug detect PC...

Page 45: ...ples Figure 2 16 PC and storage device connection to the Stratix V GX FPGA The transmitter and receiver signals of the SATA ports are connected directly to the Stratix V GX transceiver channels to pro...

Page 46: ...blocking capacitor 1 4 V PCML PIN_K44 SATA_DEVICE_TX_n0 Differential transmit data output before DC blocking capacitor 1 4 V PCML PIN_K40 SATA_DEVICE_TX_p0 Differential transmit data output before DC...

Page 47: ...CML PIN_K1 SATA_HOST_RX_p0 Differential receive data input after DC blocking capacitor 1 4 V PCML PIN_K2 SATA_HOST_TX_p1 Differential transmit data output before DC blocking capacitor 1 4 V PCML PIN_H...

Page 48: ...artus Prime project files include Quartus Prime Project File qpf Quartus Prime Setting File qsf Top Level Design File v External PLL Controller v Synopsis Design Constraints file sdc Pin Assignment Do...

Page 49: ...rding to their design requirements When users complete the settings the System Builder will generate two major files which include top level design file v and the Quartus Prime setting file qsf The to...

Page 50: ...tion provides the detail procedures on how the System Builder is used Install and launch the System Builder The System Builder is located in the directory Tools SystemBuilder in the System CD Users ca...

Page 51: ...the target board type and input project name as show in 1Figure 3 3 Project Name Specify the project name as it is automatically assigned to the name of the top level design entity Figure 3 3 The Qua...

Page 52: ...are not necessary in your design To use the DDR3 controller please refer to the DDR3 SDRAM demonstration in Chapter 6 Figure 3 4 System Configuration Group Programmable Oscillator There are two exter...

Page 53: ...elves Figure 3 5 External Programmable Oscillators Project Setting Management The System Builder also provides functions to restore default setting loading a setting and saving users board configurati...

Page 54: ...lator controller IP 3 Project name qpf Quartus Prime Project File 4 Project name qsf Quartus Prime Setting File 5 Project name sdc Synopsis Design Constraints file for Quartus Prime 6 Project name htm...

Page 55: ...DE5 Net User Manual www terasic com June 20 2018 55 For CDCM61001 and CDCM61004 the Controller will be instantiated in the Quartus Prime top level file as listed below...

Page 56: ...DE5 Net User Manual www terasic com June 20 2018 56 If dynamic configuration for the oscillator is required users need to modify the code according to users desired behavior...

Page 57: ...8MB CFI flash device Each flash device has a 16 bit data bus and the two combined flash devices allow for a 32 bit flash memory interface For the factory default code to run correctly and update desig...

Page 58: ...MAX_RST button if board is already powered on 5 When configuration is completed the green Configure Done LED will light If there is error the red Configure Error LED will light 4 4 3 3 F Fl la as sh h...

Page 59: ...program_bashrc_ub2 file as shown in 144H144HFigure 4 2 Figure 4 2 Disable elf translation and programming If your design includes a NIOS II processor and the NIOS II program is stored on external memo...

Page 60: ...cated in the CD folder Demonstrations Hello 4 4 4 4 R Re es st to or re e F Fa ac ct to or ry y S Se et tt ti in ng gs s This section describes how to restore the original factory contents to the flas...

Page 61: ...g the FACTORY_LOAD dip in SW5 to the 1 position 9 Power on the FPGA Board and the Configure Done LED should light Except for programming the Flash with the default code PFL the batch file also writes...

Page 62: ...vanced DSPLL circuitry to provide a low jitter clock at any frequency The Si570 are user programmable to any output frequency from 10 to 945 MHz and select frequencies to 1400 MHz with 1ppb resolution...

Page 63: ...gram the output frequency through the I2C interface using the following procedure 6 Freeze the DCO bit 4 of Register 137 7 Write the new frequency configuration RFREQ HSDIV and N1 to Register 7 12 8 U...

Page 64: ...ference Frequency RST_REG NewFreq Freeze M Freeze VCADC RECALL 137 Reference Frequency Freeze DCO 149H149HTable 5 2 lists the register settings for some common used frequency Table 5 2 Si570 Register...

Page 65: ...ult output frequency is 100 MHZ Users can change the output frequency by the following control pins 1 PR0 and PR1 2 OD0 OD1 and OD2 3 RSTN 4 CE 5 OS0 and OS1 The following table lists the frequency wh...

Page 66: ...respectively 5 5 2 2 S Si i5 57 70 0 E Ex xa am mp pl le e b by y R RT TL L In this section we will demonstrate how to use the Terasic Si570 Controller implemented in Verilog to control the Si570 pro...

Page 67: ...c_bus_controller based on user desired frequency Once i2c_bus_controller receives this data it will transfer these settings to Si570 via serial clock and data bus using I2C protocol The registers in S...

Page 68: ...amed iFREG_MODE in Si570 controller The specified settings with corresponding frequencies are listed in Table 5 4 For example setting iFREG_MODE as 3 b110 will configure Si570 to output 655 53 MHz clo...

Page 69: ...six clock frequencies are not desired you can perform the following steps to modify Si570 controller 1 Open i2c_reg_controller v 2 Locate the Verilog code shown below always begin case iFREQ_MODE 3 h...

Page 70: ...8 b0000_0100 fdco 28 h004_E200 end 3 h4 312 5Mhz begin new_hs_div 4 b0100 new_n1 8 b0000_0100 fdco 28 h004_E200 end 3 h5 322 265625Mhz begin new_hs_div 4 b0100 new_n1 8 b0000_0100 fdco 28 h005_0910 e...

Page 71: ...le you want to get a 133 5 mhz clock then fdco 133 5 x 4 x 10 x 64 341760d 0x53700 Find a mode in this RTL code section and modify these three parameters as shown below new_hs_div 3 b100 new_n1 4 b101...

Page 72: ...nishes users can change settings in Si570_controller v shown below initial_config initial_config iCLK iCLK system clock 50mhz iRST_n iRST_n system reset oINITIAL_START initial_start iINITIAL_ENABLE 1...

Page 73: ...igure the Si570 Observe LED3 status 5 5 3 3 S Si i5 57 70 0 a an nd d C CD DC CM M P Pr ro og gr ra am mm mi in ng g b by y N Ni io os s I II I This demonstration shows how to use the Nios II processo...

Page 74: ...should be followed with the choice number Figure 5 7 Menu of Demo Program In temperature test the program will display local temperature and remote temperature The remote temperature is the FPGA tempe...

Page 75: ...roject directory Nios_BASIC_DEMO Nios II Eclipse Nios_BASIC_DEMO Software Nios II IDE Project Compilation Before you attempt to compile the reference design under Nios II Eclipse make sure the project...

Page 76: ...ogramming PLL CDCD61004 test please input key 1 and press Enter in the nios terminal first then select the desired output frequency as shown in 158H158H Figure 5 9 For programming PLL Si570 test pleas...

Page 77: ...DE5 NET User Manual 77 www terasic com June 20 2018 Figure 5 9 CDCM 61004 Demo Figure 5 10 Si570 Demo...

Page 78: ...DDR3 SDRAM with Nios II Note 64 Bit Quartus Prime 16 1 2 Standard Edition or later is strongly recommended for compiling these projects 6 6 1 1 Q QD DR RI II I S SR RA AM M T Te es st t QDR II QDR II...

Page 79: ...is demonstration four QDRII SRAM controllers are sharing the FPGA resources OCT PLL and DLL and the QDRII SRAM B is configured as the master to share the resource to the other three slave QDRII SRAM A...

Page 80: ...the TCL files generated by QDRII IP by clicking Quartus menu Tools TCL Scripts Design Tools Quartus Prime 16 1 2 Standard Edition Demonstration Source Code Project directory QDRIIx4_Test Bit stream us...

Page 81: ...esult LED3 QDRII SRAM D test result 6 6 2 2 D DD DR R3 3 S SD DR RA AM M T Te es st t This demonstration presents a memory test function on the two sodimm of DDR3 SDRAM on the FPGA board The memory si...

Page 82: ...gnments for the DDR3 2 Setup correct parameters in the DDR3 controller dialog 3 Perform Analysis and Synthesis by selecting from the Quartus Prime menu Process Start Start Analysis Synthesis 4 Run the...

Page 83: ...seconds LED1 and LED2 should stop blinking and stay on to indicate that the DDR3 A and DDR3 B have passed the test respectively Table 6 2 lists the LED indicators If LED3 is not blinking it means the...

Page 84: ...hz controller The DDR3 IP generates one 800 MHz clock as SDRAM s data clock and one quarter rate system clock 800 4 200 MHz for those host controllers e g Nios II processor accessing the SDRAM In the...

Page 85: ...tion of Nios II Users can change the accessed memory target at Quartus compile time by defining the constant USE_DDR3_A for DDR3 A or constant USE_DDR3_B for DDR3 B bank After the constant is defined...

Page 86: ...install USB Blaster II driver if necessary Execute the demo batch file test_ub2 bat under the batch file folder NIOS_DDR3 demo_batch DDR3_A or NIOS_DDR3 demo_batch DDR3_B After Nios II program is down...

Page 87: ...n this demonstration For detail about this IP please refer to Altera document ug_pcie_avmm_dma pdf 7 7 1 1 P PC CI I E Ex xp pr re es ss s S Sy ys st te em m I In nf fr ra as st tr ru uc ct tu ur re e...

Page 88: ...ce ID DID in the driver INF file accordingly The PCI Express Library is implemented as a single DLL called TERASIC_PCIE_AVMM DLL This file is a 64 bits DLL With the DLL exported to the software API us...

Page 89: ...e steps below 1 Install the DE5 Net on the PCIe slot of the host PC 2 Make sure Altera Programmer and USB Blaster II driver are installed 3 Execute test bat in CDROM Demonstrations PCIe_Fundamental de...

Page 90: ...ng Update Driver Software dialog 6 In the How do you want to search for driver software dialog click Browse my computer for driver software item as shown in Figure 7 4 Click OK and then Exit to close...

Page 91: ...owse button to specify the folder where altera_pcie_din_driver inf is located as shown in Figure 7 5 Click the Next button Figure 7 5 Browse for driver software on your computer 8 When the Windows Sec...

Page 92: ...successfully dialog will appears as shown in Figure 7 7 Click the Close button Figure 7 7 Click Close when the installation of Altera PCI API Driver is complete 10 Once the driver is successfully inst...

Page 93: ...the procedures to use the SDK files in users C C project Create a 64 bit C C project Include TERASIC_PCIE_AVMM h in the C C project Copy TERASIC_PCIE_AVMM DLL to the folder where the project exe is lo...

Page 94: ...ro based index based on the matched verder ID and device ID Return Value Return a handle to presents specified PCIe card A positive value is return if the PCIe card is opened successfully A value zero...

Page 95: ...ta A buffer to retrieve the 32 bit data Return Value Return TRUE if read data is successful otherwise FALSE is returned PCIE_Write32 Function Write a 32 bit data to the FPGA Board Prototype bool PCIE_...

Page 96: ...E_Open function LocalAddress Specify the target memory mapped address in FPGA pBuffer A pointer to a memory buffer to retrieved the data from FPGA The size of buffer should be equal or larger the dwBu...

Page 97: ...urn Value Return TRUE if write data is successful otherwise FALSE is returned PCIE_ConfigRead32 Function Read PCIe Configuration Table Read a 32 bit data by given a byte offset Prototype bool PCIE_Con...

Page 98: ...nsfer in DMA In the design basic I O is used to control the BUTTON and LED on the FPGA board High speed data transfer is performed by DMA Demonstration Files Location The demo file is located in the b...

Page 99: ...Figure 7 9 Figure 7 9 FPGA board connect to PC 2 Configure FPGA with PCIE_Fundamental sof by executing the test bat 3 Install PCIe driver if necessary The driver is located in the folder CDROM Demonst...

Page 100: ...ndows_app folder execute PCIE_FUNDMENTAL exe A menu will appear as shown in Figure 7 11 Figure 7 11 Screenshot of Program Menu 7 Type 0 followed by a ENTER key to select Led Control item then input 15...

Page 101: ...8 Type 1 followed by an ENTER key to select Button Status Read item The button status will be report as shown in Figure 7 13 Figure 7 13 Screenshot of Button Status Report 9 Type 2 followed by an ENTE...

Page 102: ...Prime 16 1 2 Standard Edition Visual C 2012 Demonstration Source Code Location Quartus Project Demonstrations PCIE_Fundamental Visual C Project Demonstrations PCIe_SW_KIT PCIE_FUNDAMENTAL FPGAApplicat...

Page 103: ...f the PCIe reference design Windows Based Application Software Design The application software project is built by Visual C 2012 The project includes the following major files Name Description PCIE_FU...

Page 104: ...used in PCIE_Open are defined in TERASIC_PCIE_AVMM h If developer changes the Vender ID the Device ID and the PCI Express IP they also need to change the ID value defined in TERASIC_PCIE_AVMM h If th...

Page 105: ...the batch folder CDROM demonstrations PCIe_DDR3 Demo_batch The folder includes following files FPGA Configuration File PCIe_DDR3 sof Download Batch file test bat Windows Application Software folder w...

Page 106: ...R key to select Link Info item The PICe link information will be shown as in Figure 7 17 Gen3 link speed and x8 link width are expected Figure 7 17 Screenshot of Link Info 9 Type 3 followed by the ENT...

Page 107: ...key to select DMA DDR3 A SODIMM Memory Test item The DMA write and read test result will be report as shown in Figure 7 19 Figure 7 19 Screenshot of DDR3 A SOSIMM Memory DAM Test Result 11 Type 5 fol...

Page 108: ...roject Demonstrations PCIE_DDR3 Visual C Project Demonstrations PCIe_SW_KIT PCIe_DDR3 FPGAApplication Design Figure 7 21 shows the system block diagram in the FPGA system In the Qsys Altera PIO contro...

Page 109: ...roject is built by Visual C 2012 The project includes the following major files Name Description PCIE_DDR3 cpp Main program PCIE c Implement dynamically load for TERAISC_PCIE_AVMM DLL PCIE h TERASIC_P...

Page 110: ...FAULT_PCIE_DID used in PCIE_Open are defined in TERASIC_PCIE_AVMM h If the developer changes the Vender ID Device ID and PCI Express IP they also need to change the ID value defined in TERASIC_PCIE_AV...

Page 111: ...DE5 NET User Manual 111 www terasic com June 20 2018 The pcie link information is implemented by PCIE_ConfigRead32 API as shown below...

Page 112: ...ng transceiver channels can be verified with different data rates 10 3125 Gbps SPF A SPF B SPF C and SPF D 6 0 Gbps SATA Host 0 SATA Host 1 SATA Device 0 and SATA Device 1 Gbps PCIe Channel 0 7 8 8 2...

Page 113: ...TA loopback fixture Figure 8 2 SATA Loopback Fixture 176H174HFigure 8 3 shows the Terasic PCIe loopback fixture Figure 8 3 PCIe Loopback Fixture 177H175HFigure 8 4 shows the FPGA board with all transc...

Page 114: ...rs will be tested 5 Plug in the PCIe loopback fixture if PCIe transceivers will be tested Also make sure PCIe Mode SW7 is switched to x8 mode 6 Connect your FPGA board to your PC with an mini USB cabl...

Page 115: ...DE5 NET User Manual 115 www terasic com June 20 2018 Figure 8 5 Transceiver Loopback Test in Progress Figure 8 6 Transceiver Loopback Test Result Summary...

Page 116: ...Taiwan 30070 Email 46H46Hsupport terasic com Web 47H47Hwww terasic com DE5 Net Web 48H48HDE5 Net terasic com R Re ev vi is si io on n H Hi is st to or ry y Date Version Changes 2012 6 First publicati...

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