Apoolo-S10
User Manual
53
www.terasic.com
March 31, 2020
FMCP_REFCLK_M2C_p
PIN_BH33
Reference clock from
mezzanine module to
carrier card positive
LVDS
FMCP_GA[0]
PIN_AU35
FMCP geographical
address 0
3.3 V
*(2)
FMCP_GA[1]
PIN_AV35
FMCP geographical
address 1
3.3 V
*(2)
FMCP_SCL
PIN_AU34
Management serial clock
line
3.3 V
*(2)
FMCP_SDA
PIN_AU33
Management serial data
line
3.3 V
*(2)
FMCP_RES[0]
PIN_AJ34
Reserved
3.3 V
FMCP_RES[1]
PIN_AD34
Reserved
3.3 V
FMCP_SYNC_C2M_p
PIN_AU32
Synchronize signal from
carrier card to mezzanine
module positive
LVDS
FMCP_SYNC_M2C_p
PIN_AV33
Synchronize signal from
mezzanine module to
carrier card positive
LVDS
*(1): The FMCP_VCCIO value depends on the setting of JP2, which can
adjust the FMCP_VCCIO to
1.2V, 1.5V or 1.8V
. Please refer to section
2
.2 : “
FMCP_VCCIO and FMCP_VCCIO Select Header
” for details.
*(2): There are level shift ICs that convert FMCP_VCCIO to 3.3V between
the FPGA pins and the FMC pins.
2.7
Clock Circuit
The development board includes one 50 MHz TCXO and two programmable clock
shows the default frequencies of on-board all external clocks
going to the Stratix 10 SX FPGA.
