Terasic Apollo S10, User Manual

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Apoolo-S10
User Manual 22 www.terasic.com
March 31, 2020
2.3 General User I/O
This section describes the user I/O interface of the FPGA and HPS fabric. Please note
that the HPS and FPGA portions of the device each have their own pins. Pins are not
freely shared between the HPS and the FPGA fabric.

User Defined Push-buttons
The FPGA board includes two FPGA fabric and one HPS fabric user defined
push-buttons that allow users to interact with the Stratix 10 SX device. Each
push-button provides a high logic level or a low logic level when it is not pressed or
pressed, respectively. Table 2-5 lists the board references, signal names and their
corresponding Stratix 10 SX device pin numbers for the push-buttons of the FPGA
fabric. Table 2-6 list the information of the push-button for the HPS fabric.
Table 2-5 Push-button (FPGA fabric) Pin Assignments, Schematic Signal Names,
and Functions
Board
Reference
Schematic
Signal Name
Description I/O Standard
Stratix 10 SX
Pin Number
PB0 BUTTON0
High Logic Level when the
button is not pressed
3.0-V LVTTL PIN_AE36
PB1 BUTTON1 3.0-V LVTTL PIN_AG34
PB3 CPU_RESET_n 3.0-V LVTTL PIN_AC35
Table 2-6 Push-button (HPS fabric) Pin Assignments, Schematic Signal Names,
and Functions
Board
Reference
Schematic
Signal
Name
Description
I/O
Standard
Stratix 10 SX
Pin Number
PB6 HPS_KEY
High Logic Level when the button
is not pressed
1.8-V PIN_C28

User-Defined Dip Switch
There are two positions dip switch (SW0) on the FPGA fabric to provide additional
FPGA input control. When a position of dip switch is in the DOWN position or the
UPPER position, it provides a low logic level or a high logic level to the Stratix 10 SX
FPGA, respectively..