ADC-FMC User Manual
14
April 24, 2020
Figure 3-5 Block Diagram of AD9648
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There are three clock sources available for the ADC chip:
⚫
on-board clock generator Si5340B,
⚫
FPGA main board via FMC connector
⚫
External clock source via SMA connectors.
Developers can dynamic select the clock source via the ADC1_CK_S0/S1 pins for the first ADC
chip and the ADC2_CK_S0/S1 pins for the second ADC chip, as shown in
Table 3-2 Clock Source Selection
S1/S0
Clock Source
0/0
Si5340B
0/1
SMA
1/0
FPGA
In default, Si5340B outputs 125MHz clock on OUT0 and OUT1 port. OUT0 provides reference
clock for the first ADC chip, and OUT1 provides reference clock for the second ADC chip.
Developers can modify the output frequency by configure Si5340B via its I2C interface.
If SMA clock source is selected, developers need to provide clock source via SMA connector.
Summary of Contents for ADC-FMC
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