TENX TECHNOLOGY TM57PA20 User Manual Download Page 7 | Manualshive

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Advance Information

UM-TM57PA20&40_E
8 Bit Microcontroller

6

tenx technology, inc.

Preliminary

Rev 1.3, 2009/10/19

FUNCTIONAL DESCRIPTION

1. CPU Core

1.1 Clock Scheme and Instruction Cycle

The system clock is internally divided by two to generate Q1 state and Q2 state for each instruction
cycle. The Programming Counter (PC) is updated at Q1 and the instruction is fetched from program
ROM and latched into the instruction register in Q2. It is then decoded and executed during the
following Q1-Q2 cycle. Branch instructions take two cycles since the fetch instruction is ‘flushed’ from
the pipeline, while the new instruction is being fetched and then executed.

Fetch

Execute

Branch

Instruction

Instruction

Pipeline

Flow

Fetch

Execute

Fetch

Flush
Fetch

Execute

Instruction

Cycle

F

OSC

Q1

Q2

Q1

Q2

Q1

Q2

Q1

Q2

Q1

Q2

Q1

Q2

1.2 Addressing Mode

There are two Data Memory Planes in CPU, R-Plane and F-Plane. The registers in R-Plane are write-
only. The “MOVWR” instruction copy the W-register’s content to R-Plane registers by direct addressing
mode.

The lower locations of F-Plane are reserved for the SFR. Above the SFR is General Purpose Data
Memory, implemented as static RAM. F-Plane can be addressed directly or indirectly. Indirect
Addressing is made by INDF register. The INDF register is not a physical register. Addressing INDF
actually addresses the register whose address is contained in the FSR register (FSR is a pointer). The
first half of F-Plane is bit-addressable, while the second half of F-Plane is not bit-addressable.

R-Plane

F-Plane

00

00

SFR

Bit

Addressable

MOVWR

Instruction

1F

Write

Only 20

RAM

Bit Addressable

27

28

RAMBANK=0

RAMBANK=1

Bit Addressable

Bit Addressable

3F

3F

40

RAMBANK=0

RAMBANK=1

7F

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Summary of Contents for TM57PA20

Page 1: ...nformation tenx technology inc Preliminary Rev 1 3 2009 10 19 TM57PA20 TM57PA40 8 Bit Microcontroller User Manual Tenx reserves the right to change or discontinue this product without notice tenx technology inc ...

Page 2: ...Register SYSCFG 9 2 3 PROM Re use 10 2 4 Power Down Mode 10 3 Peripheral Functional Block 11 3 1 Watchdog WDT Wakeup WKT Timer 11 3 2 Timer0 8 bit Timer Counter with Pre scale PSC 12 3 3 Timer1 8 bit Timer with Pre scale PSC 13 3 4 8 2 bit PWM 14 3 5 12 bit ADC 16 3 6 System Clock Oscillator 18 3 7 BUZZER Output 19 4 I O Port 21 4 1 PA0 2 21 4 2 PA3 6 PB0 1 PD0 7 22 4 3 PA7 22 MEMORY MAP 23 F Plan...

Page 3: ...c Preliminary Rev 1 3 2009 10 19 PACKAGING INFORMATION 42 20 DIP Package Dimension 42 20 SOP Package Dimension 43 20 SSOP Package Dimension 44 16 DIP Package Dimension 45 16 SOP Package Dimension 46 16 SSOP Package Dimension 47 8 DIP Package Dimension 48 8 SOP Package Dimension 49 ...

Page 4: ...solution 8 12 bit ADC with 8 channel input 9 Buzzer output 10 Watchdog Wakeup Timer On chip Timer based on internal RC oscillation 13 140mS wakeup time 11 Reset Power On Reset Watchdog Reset Low Voltage Reset External pin Reset 12 System Clock Mode Slow Crystal 32KHz Fast Crystal 455KHz 24MHz Internal RC 4MHz External RC 13 Operation Voltage Low Voltage Reset Level to 5 5V 14 Instruction set 36 In...

Page 5: ...BUZZER PD1 6 20 SOP 15 PD7 ADC4 PD2 7 20 DIP 14 PA5 ADC5 PD3 8 20 SSOP 13 PA0 PWM0 PD4 9 12 PB0 ADC7 PWM1 PD5 10 11 PD6 ADC6 TCOUT VSS 1 U 16 VDD Xrc Xin PA4 2 TM57PA20 15 PA6 ADC0 INT0 Xout PA3 3 TM57PA40 14 PA1 ADC1 INT1 VPP nRESET INT2 PA7 4 16 SOP 13 PA2 ADC2 T0I T1OUT PD0 5 16 DIP 12 PB1 ADC3 BUZZER PD1 6 16 SSOP 11 PD7 ADC4 PD2 7 10 PA5 ADC5 PD3 8 9 PA0 PWM0 VSS 1 U 8 VDD Xrc Xin PA4 2 TM57P...

Page 6: ... are assignable by software PA7 I Schmitt trigger input nRESET I External active low reset Xin Xout Crystal Resonator oscillator connection for system clock Xrc External RC oscillator connection for system clock VDD VSS P Power input pin and ground VPP I PROM programming high voltage input INT0 2 I External interrupt input T0I I Timer0 s input in counter mode T1OUT O Timer1 match output T1OUT togg...

Page 7: ...cute Instruction Cycle FOSC Q1 Q2 Q1 Q2 Q1 Q2 Q1 Q2 Q1 Q2 Q1 Q2 1 2 Addressing Mode There are two Data Memory Planes in CPU R Plane and F Plane The registers in R Plane are write only The MOVWR instruction copy the W register s content to R Plane registers by direct addressing mode The lower locations of F Plane are reserved for the SFR Above the SFR is General Purpose Data Memory implemented as s...

Page 8: ... the ALU may affect the values of Carry C Digit Carry DC and Zero Z Flags in the STATUS register The C and DC flags operate as a Borrow and Digit Borrow respectively in subtraction 1 5 STATUS Register This register contains the arithmetic status of ALU and the Reset status The STATUS register can be the destination for any instruction as with any other register If the STATUS register is the destin...

Page 9: ...ned by F W If the corresponding interrupt enable bit has been set INTE it would trigger CPU to service the interrupt CPU accepts interrupt in the end of current executed instruction cycle In the mean while A CALL 001 instruction is inserted to CPU and i flag is set to prevent recursive interrupt nesting The i flag is cleared in the instruction after the RETI instruction That is at least one instru...

Page 10: ...ister SYSCFG The System Configuration Register SYSCFG is located at ROM address FFCh The SYSCFG determines the option for initial condition of MCU It is written by PROM Writer only User can select clock source LVR threshold voltage and chip operation mode by SYSCFG register The 13th bit of SYSCFG is code protection selection bit If this bit is 0 the data in PROM will be protected when user read PR...

Page 11: ...e SYSCFG if nPROTECT 0 and nREUSE 1 the Code protection area is first half of PROM This allows the Writer tool to write then verify the Code during the Re use Code programming After the Re use Code being written into the PROM s second half user should write nREUSE control bit to 0 In the mean while the Code protection area becomes the whole PROM except the Reserved Area PROM nREUSE 1 PROM nREUSE 0...

Page 12: ...are the same internal RC Timer The overflow period of WDT WKT can be selected from 13mS to 140mS The WDT WKT is cleared by the CLRWDT instruction If the Watchdog Reset is enabled WDTE 1 the WDT generates the chip reset signal even in sleep mode otherwise the WKT only generates overflow time out interrupt If WDTE 0 and WKTIE 0 Wakeup interrupt disable the internal RC Timer stops for power saving ...

Page 13: ...bit wide register of F Plane It can be read or written as any other register of F Plane Besides Timer0 increases itself periodically and automatic roll over base on the pre scaled clock source which can be the instruction cycle or T0I input The Timer0 increase rate is determined by Timer0 Pre Scale TM0PSC register in R Plane The Timer0 can generate interrupt TM0I when it rolls over ...

Page 14: ... of F Plane It can be read or written as any other register of F Plane Besides Timer1 increases itself periodically and automatic reloads a new offset value TM1RELD while it rolls over base on the pre scaled instruction clock The Timer1 increase rate is determined by Timer1 Pre Scale TM1PSC register in R Plane The Timer1 can generate interrupt TM1I and T1OUT toggle signal when it rolls over ...

Page 15: ...ck divided by 256 instead of System Clock divided by 1024 which means the PWM is 4 times fast than normal The advantage of higher PWM frequency is that the post RC filter can transform the PWM signal to more stable DC voltage level The PWM output signal reset to low level whenever the 8 bit base counter matches the 8 bit MSB of PWM duty register PWMDUTY When the base counter rolls over the 2 bit L...

Page 16: ...technology inc Preliminary Rev 1 3 2009 10 19 PWM example code movlw 01111111b movwf 0ch set PWM0DUTY 9 2 8 b01111111 movlw 11000000b movwf 0dh set PWM0DUTY 1 0 2 b11 movlw 01000000b movwr 0bh enable PWM0 output to PA0 PWM0_OUT movlw 00h movwr 0bh disable PWM0 PWM0_OUT ...

Page 17: ...requency which must be less than 2MHz User then launch the ADC conversion by set the ADCSTART control bit After end of conversion H W automatic clears the ADCSTAT bit User can poll this bit to know the conversion status The nADC_IE control register is used for ADC pin type setting user can write the corresponding bit to 0 when the pin is used as a ADC input The setting can disable the pin logical ...

Page 18: ...hnology inc Preliminary Rev 1 3 2009 10 19 movwr 12h set ADC7 input enable nADC_IE movlw 00010000b movwr 0ch set ADC clock is instruction cycle 64 ADCCLKS bsf 11h 3 start ADC conversion ADCSTART ADC_LOOP btfsc 11h 3 goto ADC_LOOP wait ADCSTART go LOW read ADCQ 11 0 ADCDQ ...

Page 19: ...ected by setting the CLKS in the SYSCFG register In Slow Fast Crystal mode a crystal or ceramic resonator is connected to the Xin and Xout pins to establish oscillation In external RC mode the external resistor and capacitor determine the oscillation frequency In the internal RC mode the on chip oscillator generates 4MHz system clock XIN XOUT C1 C2 External Oscillator Circuit Crystal or Ceramic Ex...

Page 20: ...r enable control bit BUZ_EN and the Buzzer output pin enable control bit BUZ_OUT Buzzer Counter Buffer Reload Buzzer Output Buzzer Data Change Before After Buzzer Data Change Before After Buzzer Disable Buzzer Enable BUZ_PROD 5 0 determines output frequency Frequency calculation is as follows FBZ fOSC 2 Instruction Cycle Divider BUZ_PROD 1 Output frequency calculation CPU Clock fosc 8192KHz Instru...

Page 21: ... Rev 1 3 2009 10 19 FBZ 8192KHz 2 32 9 1 12 8 KHz BUZZER example code movlw 10000000b movwr 0bh enable BUZZER output to PD1 BUZ_OUT movlw 11001001b fosc 2 32 BUZ_PSC movwr 10h Period 9 BUZ_PROD movlw 80h movwr 0ch enable BUZZER counting BUZ_EN movlw 00h movwr 0ch disable BUZZER counting BUZ_EN ...

Page 22: ...ucture is that the output rise time can be much faster than pure open drain structure S W sets PAE 1 to use the pin in CMOS push pull output mode Reading the pin data PAD has different meaning In Read Modify Write instruction CPU actually reads the output data register In the others instructions CPU reads the pin state The so called Read Modify Write instruction includes BSF BCF and all instructio...

Page 23: ...0 1 PD0 7 These pins are almost the same as PA0 2 except they do not support pseudo open drain mode They can be used in pure open drain mode instead 4 3 PA7 PA7 can be only used in Schmitt trigger input mode The pull up resistor is always connected to this pin MN Drive PAE PAD PA3 6 nPAPU 0 MN Drive MN Drive MR Drive MP Drive ...

Page 24: ...r1 interrupt event pending flag set by H W while Timer1 overflow TM1I 09 5 W 0 write 1 clear this flag write 1 no action R Timer0 interrupt event pending flag set by H W while Timer0 overflow TM0I 09 4 W 0 write 0 clear this flag write 1 no action R WKT interrupt event pending flag set by H W while WKT time out WKTI 09 3 W 0 write 0 clear this flag write 1 no action R INT2 pin PA7 interrupt event ...

Page 25: ... Bit Microcontroller 24 tenx technology inc Preliminary Rev 1 3 2009 10 19 ADCSEL 11 2 0 R W 0 ADC channel select 0 ADC0 1 ADC1 7 ADC7 RAM 20 27 R W Internal RAM Common Area 28 7F R W Internal RAM RAM Bank0 28 7F R W Internal RAM RAM Bank1 ...

Page 26: ...rain output or Schmitt trigger input 1 the pin is CMOS push pull output PBE 06 1 0 W 0 Each bit controls its corresponding pin if the bit is 0 the pin is open drain output or Schmitt trigger input 1 the pin is CMOS push pull output PDE 07 7 0 W 0 Each bit controls its corresponding pin if the bit is 0 the pin is open drain output or Schmitt trigger input 1 the pin is CMOS push pull output nPAPU 08...

Page 27: ...nput clock is Instruction Cycle divided by 128 1000 Timer1 input clock is Instruction Cycle divided by 256 TM1RELD 0d 7 0 W 0 Timer1 reload offset value while it rolls over TM1IE 0e 5 W 0 Timer1 interrupt enable 1 enable 0 disable TM0IE 0e 4 W 0 Timer0 interrupt enable 1 enable 0 disable WKTIE 0e 3 W 0 Wakeup Timer interrupt enable 1 enable 0 disable XINT2E 0e 2 W 0 INT2 pin PA7 interrupt enable 1...

Page 28: ...estination designator specifies where the result of the operation is to be placed If d is 0 the result is placed in the W register If d is 1 the result is placed in the address specified in the instruction For bit oriented instructions b represents a bit field designator which selects the number of the bit affected by the operation while f represents the address designator For literal operations k...

Page 29: ...fff 1 C DC Z Subtract W from f SWAPF f d 00 1110 dfff ffff 1 Swap nibbles in f TESTZ f 00 1000 1fff ffff 1 Z Test if f is zero XORWF f d 00 0110 dfff ffff 1 Z XOR W with f Bit Oriented File Register Instruction BCF f b 01 000b bbff ffff 1 Clear b bit of f BSF f b 01 001b bbff ffff 1 Set b bit of f BTFSC f b 01 010b bbff ffff 1 or 2 Test b bit of f skip if clear BTFSS f b 01 011b bbff ffff 1 or 2 T...

Page 30: ... If d is 0 the result is stored in the W register If d is 1 the result is stored back in register f Cycle 1 Example ADDWF FSR 0 B W 0x17 FSR 0xC2 A W 0xD9 FSR 0xC2 ANDLW Logical AND Literal k with W Syntax ANDLW k Operands k 00h FFh Operation W W AND f Status Affected Z OP Code 01 1011 kkkk kkkk Description The contents of W register are AND ed with the eight bit literal k The result is placed in ...

Page 31: ...tion if f b 0 Status Affected OP Code 01 010b bbff ffff Description If bit b in register f is 1 then the next instruction is executed If bit b in register f is 0 then the next instruction is discarded and a NOP is executed instead making this a 2nd cycle instruction Cycle 1 or 2 Example LABEL1 BTFSC FLAG 1 TRUE GOTO SUB1 FALSE B PC LABEL1 A if FLAG 1 0 PC FALSE if FLAG 1 1 PC TRUE BTFSS Test b bit...

Page 32: ...LRF Clear f Syntax CLRF f Operands f 00h 7Fh Operation f 00h Z 1 Status Affected Z OP Code 00 0001 1fff ffff Description The contents of register f are cleared and the Z bit is set Cycle 1 Example CLRF FLAG_REG B FLAG_REG 0x5A A FLAG_REG 0x00 Z 1 CLRW Clear W Syntax CLRW Operands Operation W 00h Z 1 Status Affected Z OP Code 00 0001 0100 0000 Description W register is cleared and Zero bit Z is set...

Page 33: ...1 B CNT 0x01 Z 0 A CNT 0x00 Z 1 DECFSZ Decrement f Skip if 0 Syntax DECFSZ f d Operands f 00h 7Fh d 0 1 Operation destination f 1 skip next instruction if result is 0 Status Affected OP Code 00 1011 dfff ffff Description The contents of register f are decremented If d is 0 the result is placed in the W register If d is 1 the result is placed back in register f If the result is 1 the next instructi...

Page 34: ...laced back in register f If the result is 1 the next instruction is executed If the result is 0 a NOP is executed instead making it a 2 cycle instruction Cycle 1 or 2 Example LABEL1 INCFSZ CNT 1 GOTO LOOP CONTINUE B PC LABEL1 A CNT CNT 1 if CNT 0 PC CONTINUE if CNT 0 PC LABEL1 1 IORLW Inclusive OR Literal with W Syntax IORLW k Operands k 00h FFh Operation W W OR k Status Affected Z OP Code 01 1010...

Page 35: ...ted OP Code 01 1001 kkkk kkkk Description The eight bit literal k is loaded into W register The don t cares will assemble as 0 s Cycle 1 Example MOVLW 0x5A B W A W 0x5A MOVWF Move W to f Syntax MOVWF f Operands f 00h 7Fh Operation f W Status Affected OP Code 00 0000 1fff ffff Description Move data from W register to register f Cycle 1 Example MOVWF REG1 B REG1 0xFF W 0x4F A REG1 0x4F W 0x4F MOVWR ...

Page 36: ... Cycle 2 Example RETFIE A PC TOS GIE 1 RETLW Return with Literal in W Syntax RETLW k Operands k 00h FFh Operation PC TOS W k Status Affected OP Code 01 1000 kkkk kkkk Description The W register is loaded with the eightbit literal k The program counter is loaded from the top of the stack the return address This is a two cycle instruction Cycle 2 Example CALL TABLE TABLE ADDWF PCL 1 RETLW k1 RETLW k...

Page 37: ...EG1 1110 0110 C 0 A REG1 1110 0110 W 1100 1100 C 1 RRF Rotate Right f through Carry Syntax RRF f d Operands f 00h 7Fh d 0 1 Operation C Register f Status Affected C OP Code 00 1100 dfff ffff Description The contents of register f are rotated one bit to the right through the Carry Flag If d is 0 the result is placed in the W register If d is 1 the result is placed back in register f Cycle 1 Example...

Page 38: ...B REG1 2 W 2 C Z A REG1 0 W 2 C 1 Z 1 B REG1 1 W 2 C Z A REG1 FFh W 2 C 0 Z 0 SWAPF Swap Nibbles in f Syntax SWAPF f d Operands f 00h 7Fh d 0 1 Operation destination 7 4 f 3 0 destination 3 0 f 7 4 Status Affected OP Code 00 1110 dfff ffff Description The upper and lower nibbles of register f are exchanged If d is 0 the result is placed in W register If d is 1 the result is placed in register f Cy...

Page 39: ...R ed with the eight bit literal k The result is placed in the W register Cycle 1 Example XORLW 0xAF B W 0xB5 A W 0x1A XORWF Exclusive OR W with f Syntax XORWF f d Operands f 00h 7Fh d 0 1 Operation destination W XOR f Status Affected Z OP Code 00 0110 dfff ffff Description Exclusive OR the contents of the W register with register f If d is 0 the result is stored in the W register If d is 1 the res...

Page 40: ...t PA7 VDD 3 V 0 32VDD V VDD 5 V 0 58VDD V Input High Voltage VIH PA7 VDD 3 V 0 63VDD V VDD 5 V 0 28VDD V All Input except PA7 VDD 3 V 0 27VDD V VDD 5 V 0 32VDD V Input Low Voltage VIL PA7 VDD 3 V 0 3VDD V VDD 5 V IOH 7mA 4 5 V Output High Voltage VOH All Output VDD 3 V IOH 4mA 2 7 V VDD 5 V IOL 20mA 0 5 V Output Low Voltage VOL All Output VDD 3 V IOL 10mA 0 3 V Input Leakage Current pin high IILH ...

Page 41: ...0 V to 5 5 V Parameter Conditions Min Typ Max Unit RESET Input Low width Input VDD 5 V 10 3 μs VDD 5 V WKTPSC 11 Typ 15 100 Typ 15 WDT wakeup time VDD 3 V WKTPSC 11 Typ 15 128 Typ 15 mS CPU start up time VDD 5 V 3 5 mS 5 LVR Circuit Characteristics TA 25 C VDD 5 0 V Parameter Symbol Min Typ Max Unit 1 8 2 1 2 3 V LVR reference Voltage VLVR 2 9 3 1 3 5 LVR Hysteresis Voltage VHYST 0 1 V Low Voltage...

Page 42: ...Advance Information UM TM57PA20 40_E 8 Bit Microcontroller 41 tenx technology inc Preliminary Rev 1 3 2009 10 19 ...

Page 43: ...der information IC Type XX YY C Z 1 IC TYPE TM57PA20 TM57PA40 2 XX Package Type DIP Code D SOP Code S SSOP Code SS 3 YY IC Pin Number Pin Number 8 Code 8 Pin Number 16 Code 16 Pin Number 20 Code 20 4 C Reserve Must write be C 5 Z Package material Package material Pb free Code W Package material Green Package Code G z 20 DIP Package Dimension ...

Page 44: ...Advance Information UM TM57PA20 40_E 8 Bit Microcontroller 43 tenx technology inc Preliminary Rev 1 3 2009 10 19 z 20 SOP Package Dimension ...

Page 45: ...Advance Information UM TM57PA20 40_E 8 Bit Microcontroller 44 tenx technology inc Preliminary Rev 1 3 2009 10 19 z 20 SSOP Package Dimension ...

Page 46: ...Advance Information UM TM57PA20 40_E 8 Bit Microcontroller 45 tenx technology inc Preliminary Rev 1 3 2009 10 19 z 16 DIP Package Dimension ...

Page 47: ...Advance Information UM TM57PA20 40_E 8 Bit Microcontroller 46 tenx technology inc Preliminary Rev 1 3 2009 10 19 z 16 SOP Package Dimension ...

Page 48: ...Advance Information UM TM57PA20 40_E 8 Bit Microcontroller 47 tenx technology inc Preliminary Rev 1 3 2009 10 19 z 16 SSOP Package Dimension ...

Page 49: ...Advance Information UM TM57PA20 40_E 8 Bit Microcontroller 48 tenx technology inc Preliminary Rev 1 3 2009 10 19 z 8 DIP Package Dimension ...

Page 50: ...Advance Information UM TM57PA20 40_E 8 Bit Microcontroller 49 tenx technology inc Preliminary Rev 1 3 2009 10 19 z 8 SOP Package Dimension ...

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