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UL865-N3G V2 Hardware User
Guide

1VV0301177 Rev 2– 2015-04-20

Summary of Contents for UL865N3G

Page 1: ...UL865 N3G V2 Hardware User Guide 1VV0301177 Rev 2 2015 04 20...

Page 2: ...ser Guide 1VV0301177 Rev 2 2015 04 20 Reproduction forbidden without written authorization from Telit Communications S p A All Rights Reserved Page 2 of 70 Mod 0805 2011 07 Rev 2 APPLICABILITY TABLE P...

Page 3: ...tries preserve for Telit and its licensors certain exclusive rights for copyrighted material including the exclusive right to copy reproduce in any form distribute and make derivative works of the cop...

Page 4: ...system or translated into any language or computer language in any form or by any means without prior written permission of Telit High Risk Materials Components units or third party products used in t...

Page 5: ...w 12 3 UL865 N3G V2 Mechanical Dimensions 13 4 UL865 N3G V2 module connections 14 4 1 PIN OUT 14 4 2 Debug in Production 16 4 3 Pin Layout 17 5 Hardware Commands 18 5 1 Auto Turning ON the UL865 N3G V...

Page 6: ...specifications 39 8 5 Reset signal 40 9 USB Port 41 9 1 USB 2 0 HS 41 10 SPI Port 42 10 5 SPI Connections 42 11 Serial Ports 43 11 1 MODEM SERIAL PORT 1 43 11 2 MODEM SERIAL PORT 2 45 11 3 RS232 leve...

Page 7: ...r Output 57 15 Mounting the UL865 N3G V2 on your Board 58 15 1 General 58 15 2 Module finishing dimensions 58 15 3 Recommended foot print for the application 59 15 4 Stencil 60 15 5 PCB pad design 60...

Page 8: ...eneral contact technical support to report documentation errors and to order manuals contact Telit Technical Support Center TTSC at TS EMEA telit com TS NORTHAMERICA telit com TS LATINAMERICA telit co...

Page 9: ...n The antenna connection and board layout design are the most important parts in the full product design Chapter 8 Logic Level specifications Specific values adopted in the implementation of logic lev...

Page 10: ...ning Alerts the user to important points about integrating the module if these points are not followed the module and end user equipment may fail or malfunction Tip or Information Provides advice and...

Page 11: ...bidden without written authorization from Telit Communications S p A All Rights Reserved Page 11 of 70 Mod 0805 2011 07 Rev 2 1 7 Document History Revision Date Changes Rev 0 2014 10 13 Preliminary Ve...

Page 12: ...5 N3G V2 cellular module within user application shall be done according to the design rules described in this manual IT L integrazione del modulo cellulare GSM GPRS WCDMA UL865 N3G V2 all interno del...

Page 13: ...ion forbidden without written authorization from Telit Communications S p A All Rights Reserved Page 13 of 70 Mod 0805 2011 07 Rev 2 3 UL865 N3G V2 Mechanical Dimensions The UL865 N3G V2 overall dimen...

Page 14: ...OS 1 8V Prog Data HW Flow Control 1 C109 DCD GPO O Output for Data carrier detect signal DCD to DTE GP output CMOS 1 8V 2 C125 RING GPO O Output for Ring indicator signal RI to DTE GP output CMOS 1 8V...

Page 15: ...IO_04 DVI_CLK I O GPIO04 Configurable GPIO Digital Audio Interface CLK CMOS 1 8V 29 GPIO_05 I O GPIO05 Configurable GPIO CMOS 1 8V 28 GPIO_06 SPI_SRDY I O GPIO06 Configurable GPIO ALARM SPI_SRDY CMOS...

Page 16: ...he customer application these pads include but are not limited to the following signals TXD RXD RESET GND VBATT VBATT_PA TX_AUX RX_AUX PWRMON Pin signal 38 37 VBATT VBATT_PA 32 33 35 36 46 GND 23 AGND...

Page 17: ...forbidden without written authorization from Telit Communications S p A All Rights Reserved Page 17 of 70 Mod 0805 2011 07 Rev 2 4 3 Pin Layout TOP VIEW NOTE The pins defined as NC RFU shall be consi...

Page 18: ...V2 will automatically power on itself when VBATT VBATT_PA are applied to the module V_AUX PWRMON pin will be at the high logic level and the module can be considered fully operating after 5 seconds T...

Page 19: ...er supply must be applied either at the same time on pins VBATT and VBATT_PA NOTE To guarantee a correct module s start up please check that the Power Supply is with a level 3 22V within 21mS NOTE In...

Page 20: ...n authorization from Telit Communications S p A All Rights Reserved Page 20 of 70 Mod 0805 2011 07 Rev 2 A flow chart showing the AT commands managing procedure is displayed below Modem ON Proc Discon...

Page 21: ...5 2 Turning OFF the UL865 N3G V2 The following flow chart shows the proper turnoff procedure NOTE In order to prevent a back powering effect it is recommended to avoid having any HIGH logic level sig...

Page 22: ...rmal operation of the device since it does not detach the device from the network It shall be kept as an emergency exit procedure to be done in the rare case that the device gets stuck waiting for som...

Page 23: ...ware User Guide 1VV0301177 Rev 2 2015 04 20 Reproduction forbidden without written authorization from Telit Communications S p A All Rights Reserved Page 23 of 70 Mod 0805 2011 07 Rev 2 A simple circu...

Page 24: ...0805 2011 07 Rev 2 In the following flow chart is detailed the proper restart procedure NOTE In order to prevent a back powering effect it is recommended to avoid having any HIGH logic level signal a...

Page 25: ...TT VBATT_PA signals and must fulfill the following requirements POWER SUPPLY Nominal Supply Voltage 3 8 V Normal Operating Voltage Range 3 40 V 4 20 V Extended Operating Voltage Range 3 1 V 4 50 V NOT...

Page 26: ...187 WCDMA data call Cat 8 TX 0dBm WCDMA HSDPA 22dBm 494 WCDMA data call Cat 8 TX 24dBm NOTE The electrical design for the Power supply should be made ensuring it will be capable of a peak current outp...

Page 27: ...r supply will not be suited because of the low drop out requirements When using a linear regulator a proper heat sink shall be provided in order to dissipate the power generated A Bypass low ESR capac...

Page 28: ...aks absorption In any case the frequency and Switching design selection is related to the application to be developed due to the fact the switching frequency could also generate EMC interferences For...

Page 29: ...e for the UL865 N3G V2 and damage it NOTE DON T USE any Ni Cd Ni MH and Pb battery types directly connected with UL865 N3G V2 Their use can lead to overvoltage on the UL865 N3G V2 and damage it USE ON...

Page 30: ...s If we assume that the device stays into transmission for short periods of time let s say few minutes and then remains for a quite long time in idle let s say one hour then the power supply has alway...

Page 31: ...loss but especially to avoid the voltage drops on the power line at the current peaks frequency of 216 Hz that will reflect on all the components connected to that supply introducing the noise floor...

Page 32: ...2 The power supply input cables should be kept separate from noise sensitive lines such as microphone earphone cables The insertion of EMI filter on VBATT pins is suggested in those designs where ant...

Page 33: ...nd the guidelines for a proper design The antenna and antenna transmission line on PCB for a Telit UL865 N3G V2 device shall fulfill the following requirements UL865 N3G V2 Frequency range Depending b...

Page 34: ...re that the antenna line impedance is 50 ohm Keep the antenna line on the PCB as short as possible since the antenna line loss shall be less than 0 3 dB Antenna line must have uniform characteristics...

Page 35: ...line length as short as possible thus leading to lowest power losses possible A Grounded Coplanar Waveguide G CPW line has been chosen since this kind of transmission line ensures good impedance cont...

Page 36: ...53E VNA Full 2 port calibration has been used in this measurement session A calibrated coaxial cable has been soldered at the pad corresponding to RF output a SMA connector has been soldered to the bo...

Page 37: ...tten authorization from Telit Communications S p A All Rights Reserved Page 37 of 70 Mod 0805 2011 07 Rev 2 Line input impedance in Smith Chart format once the line has been terminated to 50 load is s...

Page 38: ...e antenna is located farther than 20cm from the human body and there are no co located transmitter then the Telit FCC IC approvals can be re used by the end product If the device antenna is located cl...

Page 39: ...work at 1 8V CMOS logic levels The following table shows the logic level specifications used in the UL865 N3G V2 interface circuits Absolute Maximum Ratings Not Functional Parameter Min Max Input lev...

Page 40: ...gnal must not be used to normally shutting down the device but only as an emergency exit in the rare case the device remains stuck waiting for some network response The RESET is internally controlled...

Page 41: ...al Data 3 3V 6 VUSB AI Power sense for the internal USB transceiver 5V Accepted range 4 4V to 5 25V The USB_DPLUS and USB_DMINUS signals have a clock rate of 480 MHz The signal traces should be routed...

Page 42: ...ve ready and MRDY master ready The AP has the master role that is it supplies the clock The following table is listing the available signals PAD Signal I O Function Type Comment 44 SPI_MISO O SPI_MISO...

Page 43: ...mit microcontroller UART 3V or other voltages different from 1 8V microcontroller UART 5V or other voltages different from 1 8V Depending from the type of serial port on the OEM hardware a level trans...

Page 44: ...he UL865 N3G V2 that controls the DTE READY condition 5 GND 32 33 35 36 46 Ground Ground 6 DSR dsr_uart 3 Data Set Ready Output from the UL865 N3G V2 that indicates the module is ready 7 RTS rts_uart...

Page 45: ...to avoid a back powering effect it is recommended to avoid having any HIGH logic level signal applied to the digital pins of the UL865 N3G V2 when the module is powered off or during an ON OFF transi...

Page 46: ...ignal voltage must be less than 0V and hence some sort of level translation is always required The simplest way to translate the levels and invert the signal is by using a single chip level translator...

Page 47: ...eserved Page 47 of 70 Mod 0805 2011 07 Rev 2 An example of RS232 level adaptation circuitry could be done using a MAXIM transceiver MAX218 In this case the chipset is capable to translate directly fro...

Page 48: ...table shows the available GPIO on the UL865 N3G V2 and their state Pin Signal I O Function Type Input output current Default State ON_OFF state State during Reset Note 42 GPIO_01 I O Configurable GPI...

Page 49: ...utput current Default State ON_OFF state State during Reset Note 1 GPO_A O Configurable GPO CMOS 1 8V 1uA 1mA INPUT 0 0 Alternate function C109 DCD 2 GPO_B O Configurable GPO CMOS 1 8V 1uA 1mA INPUT 0...

Page 50: ...rk at 1 8V CMOS logic levels The following table shows the logic level specifications used in the UL865 N3G V2 interface circuits Absolute Maximum Ratings Not Functional Parameter Min Max Input level...

Page 51: ...the GPIO input pad has interface levels different from the 1 8V CMOS then it can be buffered with an open collector transistor with a 47K pull up to 1 8V NOTE In order to avoid a back powering effect...

Page 52: ...of GPIO_08 to be enabled using the AT GPIO 8 0 2 command In the UL865 N3G V2 modules the STAT_LED needs an external transistor to drive an external LED Therefore the status indicated in the following...

Page 53: ...unction is enabled and vice versa 13 6 RTC Bypass out The VRTC pin brings out the Real Time Clock supply which is separate from the rest of the digital part allowing having only RTC going on when all...

Page 54: ...15 of the UL865 N3G V2 The on board DAC is a 10 bit converter able to generate an analogue value based on a specific input in the range from 0 up to 1023 However an external low pass filter is necessa...

Page 55: ...C An AT command is available to use the DAC function The command is AT DAC enable value value scale factor of the integrated output voltage 0 1023 10 bit precision it must be present if enable 1 Refer...

Page 56: ...lowing table is showing the ADC characteristics Min Typical Max Units Input Voltage range 0 1 2 Volt AD conversion 10 bits Input Resistance 1 Mohm Input Capacitance 1 pF The signal is available on the...

Page 57: ...ulated power supply output is provided in order to supply small devices from the module The signal is present on Pad 43 and it is in common with the PWRMON module powered ON indication function This o...

Page 58: ...A All Rights Reserved Page 58 of 70 Mod 0805 2011 07 Rev 2 15 Mounting the UL865 N3G V2 on your Board 15 1 General The UL865 N3G V2 modules have been designed to be compliant with a standard lead free...

Page 59: ...ge 59 of 70 Mod 0805 2011 07 Rev 2 15 3 Recommended foot print for the application In order to easily rework the UL865 N3G V2 is suggested to consider on the application a 1 5 mm placement inhibited a...

Page 60: ...ved Page 60 of 70 Mod 0805 2011 07 Rev 2 15 4 Stencil Stencil s apertures layout can be the same of the recommended footprint 1 1 we suggest a thickness of stencil foil 120 m 15 5 PCB pad design Non s...

Page 61: ...A All Rights Reserved Page 61 of 70 Mod 0805 2011 07 Rev 2 15 6 Recommendations for PCB pad dimensions mm It is not recommended to place via or micro via not covered by solder resist in an area of 0 3...

Page 62: ...her temperatures which are occurring at the lead free process This issue should be discussed with the PCB supplier Generally the wettability of tin lead solder paste on the described surface plating i...

Page 63: ...min Temperature Max Tsmax Time min to max ts 150 C 200 C 60 180 seconds Tsmax to TL Ramp up Rate 3 C second max Time maintained above Temperature TL Time tL 217 C 60 150 seconds Peak Temperature Tp 24...

Page 64: ...hout written authorization from Telit Communications S p A All Rights Reserved Page 64 of 70 Mod 0805 2011 07 Rev 2 16 Packing system 16 1 Packing on tray The UL865 N3G V2 modules are packaged on tray...

Page 65: ...UL865 N3G Hardware User Guide 1VV0301177 Rev 2 2015 04 20 Reproduction forbidden without written authorization from Telit Communications S p A All Rights Reserved Page 65 of 70 Mod 0805 2011 07 Rev 2...

Page 66: ...Hardware User Guide 1VV0301177 Rev 2 2015 04 20 Reproduction forbidden without written authorization from Telit Communications S p A All Rights Reserved Page 66 of 70 Mod 0805 2011 07 Rev 2 16 2 Packi...

Page 67: ...tomer has to take care of the following conditions a The shelf life of the Product inside of the dry bag is 12 months from the bag seal date when stored in a non condensing atmospheric environment of...

Page 68: ...Same cautions have to be taken for the SIM checking carefully the instruction for its use Do not insert or remove the SIM when the product is in power saving mode The system integrator is responsible...

Page 69: ...r sent appareil est conforme aux CNR d Industrie Canada applicables aux appareils radio exempts de licence L exploitation est autoris e aux deux conditions suivantes 1 l appareil ne doit pas produire...

Page 70: ...een the equipment and receiver Connect the equipment into an outlet on a circuit different from that to which the receiver is connected Consult the dealer or an experienced radio TV technician for hel...

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