
Last update: 2002.0806
The specification is subject to change without notice.
16
D4110637B
9. Timing Chart
9-1. Digital output timing
(1) H rate (Under shutter OFF)
TIA/EIA-644 (LVDS)
Driver output voltage: Plus/minus 350mV [Differential output] / 100-ohm
Total clock counts
1328CLK / 1H (33.2 micro s)
DATA counts
1004CLK / 1H (25.1 micro s)
CLK
25.0ns
(2) H rate (Under shutter ON, for 1H only at the starting of readout)
TIA/EIA-644 (LVDS)
Driver output voltage: Plus/minus 350mV [Differential output] / 100-ohm
Total clock counts
1620CLK / 1H (40.5 micro s)
DATA counts
1004CLK / 1H (25.1 micro s)
CLK
25.0ns
Under electric shutter ON, one HD period only at the end of exposure gets
longer by 292CLK (7.3 micro s). Don’t synchronize camera with internal
HD by PLL circuit or others. Be sure to use CLK-output based on HD/VD
at the start of capturing images.
CLK
DATA
HD
235CLK
1004CLK
1328CLK
25.0ns
86CLK
3CLK
CLK
DATA
HD
235CLK
1004CLK
1620CLK
25.0ns
86CLK
295CLK
Caution
!
!
!
!