Tektronix Tektronix SPG8000, Technical Reference

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Performance veri fi cation
Test record Photocopy this table and use it to record the performance test results.
Table 30: SPG8000 base unit test record
Instrument Serial Number:
Temperature:
Date of Calibration: Certi fi cate Number:
RH %:
Technician:
Performance test –Min +Max Measured Value Value
Master clock accuracy 9.9999987 MHz 10.0000013 MHz
NTSC Functional Genlock and
timing Pass Fail
PAL Functional Genlock and
timing Pass Fail
1080p24 Functional lock and
timing Pass Fail
Genlock ADC Bus Stuck Pass Fail
Genlock ADC Bus Short Pass Fail
Genlock Input
Minimum level 1550 2550
Maximum level 2550 3550
Gain 900 1100
LTC Positive Input Open Circuit
Loop Back
Minimum level 1250 1500
Maximum level 2200 2450
Gain
850 1050
LTC Negative Input Open Circuit
Loop Back
Minimum level 1250 1500
Maximum level 2200 2450
Gain 850 1050
LTC Positive Input Terminated
Loop Back Gain 400 525
LTC Negative Input Terminated
Loop Back Gain
400 525
SPG8000 Speci fi cations and Performance Veri fi cation 27