Tektronix SPG300, Service Manual, Page: 69 / 176

Theory of Operation
SPG600 & SPG300 Sync Pulse Generators Service Manual
3-3
Line Memory.
The line memory is a part of the FPGA and contains the active part
of the line data of the test signal. It can store up to four line data.
Frame Memory. The frame memory contains a series of pointers that control the
order of the video lines stored in the Line Memory, which are used to produce
digital signals.
Overlay Memory. The overlay memory generates timing to multiplex the line
memory data and the overlay data used for an ID text and logo overlay.
Delay Counter.
The delay counter in the FPGA sets the timing of each channel.
Signal Generator.
This block builds complete test signal sequence with black and
line data according to the frame memory.
Embedded Packet Generator. This block generates 16-channel embedded audio
data.
Serializer.
This block converts a 10-bit parallel data to SDI signal.
Audio Generator
The audio generator consists of the following blocks:
Audio Memory.
The audio memory contains the data for both analog and AES/EBU
packet generators.
Analog Waveform Generator. The generator obtains the data from the audio
memory and builds the analog waveform.
D/A Converter and Amplifier.
This block contains two set of D/A converters and
amplifiers for generating left and right signals. The D/A converter receives the data
from the analog waveform generator and converts them to an analog signal. The
amplifier amplifies the signal to the desired level.
AES/EBU Packet Generator and Word Clock. The packet generator creates the
AES/EBU packets based on the memory contents. Word clock generates a 48 kHz
clock signal.
Drivers. This block contains four driver circuits for AES/EBU and a driver for the
word clock. The drivers set the output amplitude and impedance.
A20 Front-Panel Board
The A20 Front-Panel board consists of the rubber contact switches and three LEDs.