Tektronix 1740A Series, User Manual

Page: 87 / 368

Circuit Theory
1740A/1750A/1760 – Series Service Manual
3–23
Diagram 16 Demodulator
Incoming chrominance is band-pass filtered, clamped at sync tip time, and
compared to the phase-shifted, regenerated subcarrier signal for demodulation.
Subcarrier signal is quadrature shifted (90
°
) before input to the R–Y (V)
demodulator. In addition, for PAL applications, and any time the front-panel
selected Test Circle is enabled, a V–Axis switcher shifts the subcarrier input by
180
°
for alternate lines.
Output signal from the Demodulators is low-pass filtered and amplified prior to
driving the Horizontal and Vertical Output Amplifiers.
V-axis switching displays the PAL signal with the –V lines overlayed on the +V
lines. The resulting display appears as though only the +V signal is displayed,
similar to an NTSC display. This display evaluates relative differences between
the +V and –V lines, just as the signal is decoded in a PAL receiver. The
Microprocessor pulls the Preset input of U3B (a D-type flip-flop) high, which
allows the horizontal sync, clock pulses to toggle its outputs at a line rate. The
D input is controlled by another flip-flop, U28A (on Diagram 14), which has
identified the +V lines (for PAL) in the Subcarrier Regenerator.
The flip-flop outputs drive Q5 and Q6. A high output turns on the correspond-
ing transistor to shunt the signal at its collector to ground. This alternately
grounds and drives the + and – carrier inputs on the V Demodulator with
subcarrier to demodulate the –V lines 180
°
away from the +V lines.
The chrominance demodulators, U26 and U28, are double-balanced demodula-
tors, whose outputs are voltages proportional to the phase difference between the
signal input (pins 1 and 4) and the carrier input (pins 8 and 10). The signal
inputs are driven by chrominance from the Chroma Amplifier (Diagram 13).
The carrier inputs are driven by a continuous sine wave, at subcarrier frequency,
from the Subcarrier Regenerator (Diagram 14). T1 is a balanced transformer
driving an LRC delay network, with L3 adjusted for PAL quad phase and C26
adjusted for NTSC quad phase. The V–Axis Switching circuit, when operating,
determines which carrier input of the R–Y (V) Demodulator is driven by
subcarrier. When NTSC is selected, U3B Preset input is forced low to turn on
Q6 and ground the + Carrier input.
The demodulator gains are set by R36 for R–Y and R52 for B–Y. R36 is the +V
Balance which provides offset voltage for pins 2 and 3. The bias is controlled by
the Center Dot Position Clamp circuits.
V-Axis Switcher
Chrominance
Demodulators
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