TAM-3517 HARDWARE MANUAL rev B
July 3 2012, TechNexion
36
Pin #
Ball #
Pin Name
mode V
type description
143
M2
GPMC_nCS4
0
3.3
O
GPMC Chip Select 4
Sys_ndmareq1
1
I
External DMA request 1
(system expansion). Level
(active low) or edge (falling)
selectable.
Gpt9_pwm_evt
3
IO
PWM or event for GP timer
9
GPIO_55
4
IO
General-purpose IO 55
Safe_mode
7
144
M4
GPMC_nCS2
0
O
GPMC Chip Select 2
Gpt9_pwm_evt
2
IO
PWM or event for GP timer
9
GPIO_53
4
IO
General-purpose IO 53
Safe_mode
7
145
M3
GPMC_nCS3
0
3.3
O
GPMC Chip Select 3
Sys_ndmareq0
1
I
External DMA request 0
(system expansion). Level
(active low) or edge (falling)
selectable.
Gpt10_pwm_evt
2
IO
PWM or event for GP timer
10
GPIO_54
4
IO
General-purpose IO 54
Safe_mode
7
146
F7
GPMC_A4
0
3.3
O
GPMC_Address bit 4
GPIO_37
4
IO
General-purpose IO 37
Safe_mode
7
147
G6
GPMC_A10
0
3.3
O
GPMC Address bit 10
Sys_ndmareq3
1
I
External DMA request 3
(system expansion). Level
(active low) or edge (falling)
selectable.
GPIO_43
4
IO
General-purpose IO 43
Safe_mode
7
148
M1
GPMC_nCS5
0
3.3
O
GPMC Chip Select 5
Sys_ndmareq2
1
I
External DMA request 2
(system expansion). Level
(active low) or edge (falling)
selectable.
Gpt10_pwm_evt
3
IO
PWM or event for GP timer
10
GPIO_56
4
IO
General-purpose IO 56
Safe_mode
7
149
F2
GPMC_A8
0
3.3
O
GPMC_Address bit 8
GPIO_41
4
IO
General-purpose IO 41
Safe_mode
7
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