TechNexion PICO-IMX6, Hardware Manual

Page: 27 / 64

PICO-IMX6 REV. A1. HARDWARE MANUAL
– VER 1.01 – JAN 28 2016
Page 27 of 64
3. PICO Compute Module Connector Interfaces
3.1 Ethernet
The PICO-IMX6 implements a triple speed 10/100/1000 Mbit/s Ethernet MAC compliant with the
IEEE802.3-2002 standard. The MAC layer provides compatibility with half- or full-duplex 10/100 Mbit/s
Ethernet LANs and full-duplex gigabit Ethernet LANs.
The Ethernet MAC supports the following features:

Implements the full 802.3 specification with preamble/SFD generation, frame padding generation,
CRC generation and checking

Supports zero-length preamble

Dynamically configurable to support 10/100 Mbit/s and gigabit operation

Supports 10/100 Mbit/s full-duplex and configurable half-duplex operation

Supports gigabit full-duplex operation

Compliant with the AMD magic packet detection with interrupt for node remote power
management

Seamless interface to commercial ethernet PHY devices via one of the following:
o
4-bit Media Independent Interface (MII) operating at 2.5/25 MHz.
o
4-bit non-standard MII-Lite (MII without the CRS and COL signals) operating at 2.5/25
MHz.
o
2-bit Reduced MII (RMII) operating at 50 MHz.
o
(Double data rate) 4-bit Reduced GMII (RGMII) operating at 125 MHz.
For additional details, please refer to the “10/100/1000-Mbps Ethernet MAC (ENET)” chapter of the
“i.MX6 Reference Manual”.
Table 6 - Ethernet Signal Description
PIN
CPU
BALL
CPU PAD NAME Signal V I/O Description
X1_33 V20 ENET_MDC RGMII_MDC 3V3
Management data clock
reference
X1_35 V23 ENET_MDIO RGMII_MDIO 3V3 Management data
X1_37 W22 ENET_RXD1 RGMII_nRST 3V3 Ethernet reset
X1_39 V21 ENET_TX_EN RGMII_INT 3V3 Ethernet interrupt output
X1_41 V22 ENET_REF_CLK RGMII_REF_CLK 3V3
Synchronous Ethernet
recovered clock
X1_43 C23 RGMII_TX_CTL RGMII_TXEN 1V5 RGMII transmit enable
X1_45 D22 RGMII_RX_CTL RGMII_RXDV 1V5 RGMII receive data valid
X1_49 D21 RGMII_TXC RGMII_TXCLK 1V5 O RGMII transmit clock
X1_51 C22 RGMII_TD0 RGMII_TXD0 1V5 O RGMII transmit data 0
X1_53 F20 RGMII_TD1 RGMII_TXD1 1V5 O RGMII transmit data 1
X1_55 E21 RGMII_TD2 RGMII_TXD2 1V5 O RGMII transmit data 2
X1_57 A24 RGMII_TD3 RGMII_TXD3 1V5 O RGMII transmit data 3
X1_61 B25 RGMII_RXC RGMII_RXCLK 1V5 I RGMII receive clock
X1_63 C24 RGMII_RD0 RGMII_RXD0 1V5 I RGMII receive data 0
X1_65 B23 RGMII_RD1 RGMII_RXD1 1V5 I RGMII receive data 1
X1_67 B24 RGMII_RD2 RGMII_RXD2 1V5 I RGMII receive data 2
X1_69 D23 RGMII_RD3 RGMII_RXD3 1V5 I RGMII receive data 3