TFT LCD MODULE
Pin
Name
Description
1
RXO0-
Negative LVDS differential data input. Channel O0 (odd)
2
RXO0+
Positive LVDS differential data input. Channel O0 (odd)
3
RXO1-
Negative LVDS differential data input. Channel O1 (odd)
4
RXO1+
Positive LVDS differential data input. Channel O1 (odd)
5
RXO2-
Negative LVDS differential data input. Channel O2 (odd)
6
RXO2+
Positive LVDS differential data input. Channel O2 (odd)
7
GND
Ground
8
RXOC-
Negative LVDS differential clock input. (odd)
9
RXOC+
Positive LVDS differential clock input. (odd)
10
RXO3-
Negative LVDS differential data input. Channel O3(odd)
11
RXO3+
Positive LVDS differential data input. Channel O3 (odd)
12
RXE0-
Negative LVDS differential data input. Channel E0 (even)
13
RXE0+
Positive LVDS differential data input. Channel E0 (even)
14
GND
Ground
15
RXE1-
Negative LVDS differential data input. Channel E1 (even)
16
RXE1+
Positive LVDS differential data input. Channel E1 (even)
17
GND
Ground
18
RXE2-
Negative LVDS differential data input. Channel E2 (even)
19
RXE2+
Positive LVDS differential data input. Channel E2 (even)
20
RXEC-
Negative LVDS differential clock input. (even)
21
RXEC+
Positive LVDS differential clock input. (even)
22
RXE3-
Negative LVDS differential data input. Channel E3 (even)
23
RXE3+
Positive LVDS differential data input. Channel E3 (even)
24
GND
Ground
25
NC
Not connection, this pin should be open.
26
AGMODE
AGMODE should be tied to ground or open.
27
VCC
+5.0V power supply
28
VCC
+5.0V power supply
29
VCC
+5.0V power supply
30
VCC
+5.0V power supply
Note (1) Connector Part No.: 093G30-B0001A(STARCONN) or FI-X30SSL-HF(JAE) or EQUIVALENT.
Note (2) The first pixel is odd.
Note (3) Input signal of even and odd clock should be the same timing.
