Teac DV-H500, Service Manual

Page: 18 / 58

2-18
2. IC19 (PCM1600 6CH DAC)
PIN DESCRIPTION
P I N N A M E I / O DESCRIPTION
1 ZERO1 O Zero Data Flag for V
OUT
1.
2 ZERO2 O Zero Data Flag for V
OUT
2.
3 ZERO3 O Zero Data Flag for V
OUT
3.
4 ZERO4 O Zero Data Flag for V
OUT
4.
5 ZERO5 O Zero Data Flag for V
OUT
5.
6 ZERO6 O Zero Data Flag for V
OUT
6.
7 AGND — Analog Ground
8 V
CC
— Analog Power Supply, +5V
9 V
OUT
6 O Voltage Output of Audio Signal Corresponding to Rch on DATA3.
10 V
OUT
5 O Voltage Output of Audio Signal Corresponding to Lch on DATA3.
11 V
OUT
4 O Voltage Output of Audio Signal Corresponding to Rch on DATA2.
12 V
OUT
3 O Voltage Output of Audio Signal Corresponding to Lch on DATA2.
13 V
OUT
2 O Voltage Output of Audio Signal Corresponding to Rch on DATA1.
14 V
OUT
1 O Voltage Output of Audio Signal Corresponding to Lch on DATA1.
15 V
COM
2 O Common Voltage Output. This pin should be bypassed with a 10
µ
F capacitor to AGND.
16 V
COM
2 O Common Voltage Output. This pin should be bypassed with a 10
µ
F capacitor to AGND.
17 AGND6 — Analog Ground
18 V
CC
6 — Analog Power Supply, +5V
19 AGND5 — Analog Ground
20 V
CC
5 — Analog Power Supply, +5V
21 AGND4 — Analog Ground
22 V
CC
4 — Analog Power Supply, +5V
23 AGND3 — Analog Ground
24 V
CC
3 — Analog Power Supply, +5V
25 AGND2 — Analog Ground
26 V
CC
2 — Analog Power Supply, +5V
27 AGND1 — Analog Ground
28 V
CC
1 — Analog Power Supply, +5V
29 AGND0 — Analog Ground
30 V
CC
0 — Analog Power Supply, +5V
31 NC I No Connection. Must be open.
32 NC I No Connection. Must be open.
33 MDO O Serial Data Output for Function Register Control Port (3)
34 MDI I Serial Data Input for Function Register Control Port (1)
35 MC IN Shift Clock for Function Register Control Port (1)
36 ML IN Latch Enable for Function Register Control Port
(1)
37 RST I System Reset, Active LOW
(1)
38 SCLKI I System Clock In. Input frequency is 256, 384, 512 or 768f
S
.
(2)
39 SCLKO O Buffered Clock Output. Output frequency is 256, 384, 512, or 768f
S
and one-half of 256, 384, 512, or 768f
S.
40 BCK IN Shift Clock Input for Serial Audio Data
(2)
41 LRCK IN Left and Right Clock Input. This clock is equal to the sampling rate, f
S
.
(2)
42 TEST — Test Pin. This pin should be connected to DGND.
(1)
43 V
DD
— Digital Power Supply, +3.3V
44 DGND — Digital Ground for +3.3V
45 DATA1 IN Serial Audio Data Input for V
OUT
1 and V
OUT
2
(2)
46 DATA2 IN Serial Audio Data Input for V
OUT
3 and V
OUT
4
(2)
47 DATA3 IN Serial Audio Data Input for V
OUT
5 and V
OUT
6
(2)
48 DATA1 IN Serial Audio Data Input for V
OUT
1 and V
OUT
2
NOTES: (1) Schmitt-Trigger input with internal pull-down, 5V tolerant. (2) Schmitt-Trigger input, 5V tolerant. (3) Tri-state output.