PIN No.
SYM BOL
I/ O
DESCRIPTION
1,31,71
2
3
4
5
6
7
8
9
10, 30
11
12
13
14
15
16
17
18
19
20
21,41,51,81,91
22
23
24
25 ~ 29
32 ~ 35
36 ~ 39
40,50,60,80,90,100
42 ~ 44
45 ~ 47
48
49
52
53
54
55
56
57
58
59
61
62
63
64
65
66
67
68
69
VDD1
RAM CEN
RAM A16
RAM A15
SDIB0
SDIB1
SDIB2
XI
XO
VSS
AVDD
SDIB3
TEST
TEST
OVFB
DTSDATA
AC3DATA
SDOB3
CPO
AVSS
VDD2
SDOA2
SDOA1
SDOA0
RAM A 14~10
OPORT 0~3
OPORT 4~7
VSS
RAAM 9~7
SDOB 2~0
SDBCK1
SDWCK1
NONPCM
CRC
M UTE
KARAOKE
SURENC
/SDBCK 0
RAM A6
RAM A5
RAM A4
/IC
TEST
RAM A3
/CSB
/CS
SO
SI
SCK
-
O
O
O
I+
I+
I+
I+
O
-
-
I+
-
-
O
O
O
O
A
-
-
O
O
O
O
O
O
-
O
O
I+
I+
O
O
O
O
O
O
O
O
O
Is
-
O
Is+
Is
Ot
Is
Is
+5V Pow er Supply(for I/Os)
External SRAM interface /CE
External SRAM interface address 16
External SRAM interface address 15
PCM input 0 to Sub DSP(not use)
PCM input 1 to Sub DSP(not use)
PCM input 2 to Sub DSP(not use)
Crystal oscillator connection(12.288M Hz)
Ground
+3.3V pow er supply (for PLL circuit)
PCM input 3 to Sub DSP(not use)
Test term inal(to be open in norm al use)
Test term inal(to be open in norm al use)
Detection of overflow at Sub DSP (not use)
Detection of DTS data (not use)
Detection of AC-3 data (not use)
PCM output from Sub DSP
Output terminal for PLL,to be connected to ground through the external analog filter circuit
Ground for PLL circuit)
+3.3V pow er supply (for core logic)
PCM output from M ain DSP (C,LFE)
PCM output from M ain DSP (LS,RS)
PCM output from M ain DSP (L,R)
External SRAM interface address 14~10
Output port for general purpose
Output port for general purpose (not use)
Ground
External SRAM interface address 9~7
PCM output from Sub DSP
Bit clock input for SDOA,SDIB,SDOB (not use)
Word clock input for SDOA,SDIB,SDOB (not use)
Detection of non-PCM data (not use)
Detection of AC-3 CRC error (not use)
Detection of auto m ute (not use)
Detection of AC-3 karaoke data (not use)
Detection of AC-3 2/0 m ode Dolby surround encoded input (not use)
Inverted SDBCK0 clock output (refer to Block diagram )
External SRAM interface address 6
External SRAM interface address 5
External SRAM interface address 4
Initial clear
Test term inal (to be ofen in norm al use)
External SRAM interface address 3
Sub DSP Chip select
M icroprocessor interface Chip select input
M icroprocessor interface serial data output
M icroprocessor interface /Sub DSP Serial data input
M icroprocessor interface /Sub DSP clock input
Dolby Digital/Pro Logic DTS DECODER (YSS912C:INPUT IC43)
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