MST6M19GL
UXGA/WSXGA+ LCD TV Controller with
VIF
Preliminary Data Sheet Version 0.1
Version 0.1
- 4 -
8/20/2007
Copyright
©
2007 MStar Semiconductor, Inc. All rights reserved.
PIN DIAGRAM (MST6M19GL)
Pin 1
13
14
17
18
21
23
25
27
28
30
32
34
36
39
41
43
15
16
19
20
22
24
26
29
31
33
35
37
38
40
42
44
45
46
47
48
50
51
52
49
REXT
HSYNC1
VSYNC1
VCLAMP
REFP
REFM
BIN1P
RIN1P
BIN0P
GIN0P
RIN0P
AVDD_33
HSYNC0
VSYNC2
SOGIN1
GIN1P
VCOM2
VCOM3
SOGIN0
GND
VSYNC0
BIN2P
SOGIN2
GIN2P
RIN2P
C1
Y1
C0
Y0
CVBS3
CVBS2
CVBS1
VCOM1
AVDD_33
CVBSOUT1
CVBSOUT0
GND
GPIOL[0]
GPIOL[1]
GPIOL[4]
XOUT
AVDD_MPLL
GND_VIFPLL
VR27
VR12
1
2
3
4
5
7
9
11
6
8
10
12
53
54
55
56
57
59
61
63
58
60
62
64
GND_RXS
SIFP
SIFM
VIFM
VIFP
AVDD_RXV
TAFC
AVDD_TAGC
GND_TAGC
TAGC
AVDD_AU
77
78
81
82
85
87
89
91
92
94
96
98
10
0
10
3
10
5
10
7
79
80
83
84
86
88
90
93
95
97
99
10
1
10
2
10
4
10
6
10
8
10
9
11
0
11
1
11
2
11
4
11
5
11
6
11
3
A
U
V
AG
A
VD
D
_A
U
LI
N
E_
IN
_0
L
LI
N
E_
IN
_0
R
LI
N
E_
IN
_1
L
LI
N
E_
IN
_1
R
AU
C
O
M
LI
N
E_
IN
_3
L
LI
N
E_
IN
_M
O
N
O
LI
N
E_
O
U
T_
3R
LI
N
E_
O
U
T_
2R
LI
N
E_
O
U
T_
1R
LI
N
E_
O
U
T_
0R
G
PI
O
D
[0
]
LI
N
E_
IN
_2
L
LI
N
E_
IN
_2
R
LI
N
E_
IN
_3
R
LI
N
E_
O
U
T_
3L
LI
N
E_
O
U
T_
2L
LI
N
E_
O
U
T_
1L
LI
N
E_
O
U
T_
0L
G
PI
O
D
[1
]
G
PI
O
D
[2
]
G
N
D
VD
D
C
W
R
Z
R
D
Z
A
LE
BA
D
R
[1
]
BA
D
R
[0
]
R
A
SZ
V
D
D
C
G
N
D
AV
D
D
_M
I
CA
SZ
W
EZ
M
AD
R
[1
1]
M
AD
R
[1
0]
65
66
67
68
69
71
73
75
70
72
74
76
11
7
11
8
11
9
12
0
12
1
12
3
12
5
12
7
12
2
12
4
12
6
12
8
M
AD
R
[9
]
M
AD
R
[8
]
M
AD
R
[7
]
M
AD
R
[6
]
M
AD
R
[5
]
M
AD
R
[4
]
M
AD
R
[1
]
M
AD
R
[3
]
M
AD
R
[2
]
M
AD
R
[0
]
180
179
176
175
172
170
168
166
165
163
161
159
157
154
152
150
178
177
174
173
171
169
167
164
162
160
158
156
155
153
151
149
148
147
146
145
143
142
141
144
192
191
190
189
188
186
184
182
187
185
183
181
140
139
138
137
136
134
132
130
135
133
131
129
24
4
24
3
24
0
23
9
23
6
23
4
23
2
23
0
22
9
22
7
22
5
22
3
22
1
21
8
21
6
21
4
24
2
24
1
23
8
23
7
23
5
23
3
23
1
22
8
22
6
22
4
22
2
22
0
21
9
21
7
21
5
21
3
21
2
21
1
21
0
20
9
20
7
20
6
20
5
20
8
D
D
C
D
_S
C
L
D
D
C
D
_S
D
A
H
PL
U
G
R
X2
P
R
X2
N
G
N
D
R
X0
P
R
X0
N
A
VD
D
_3
3
25
6
25
5
25
4
25
3
25
2
25
0
24
8
24
6
25
1
24
9
24
7
24
5
20
4
20
3
20
2
20
1
20
0
19
8
19
6
19
4
19
9
19
7
19
5
19
3
M
S
T
6
M
1
9
G
L
XX
XX
XX
XX
XX
XX
X
A
U
VR
P
AVDD_RXS
GND
G
N
D
LV
B
4P
D
I[
7]
D
I[
6]
D
I[
5]
D
I[
4]
V
D
D
P
D
I[
3]
D
I[
2]
D
I[
1]
D
I[
0]
V
D
D
P
PW
M
2
PW
M
3
R
XC
KN
R
XC
KP
R
X1
N
V
D
D
C
IC
LK
G
PI
O
T[
0]
A
U
V
R
M
G
N
D
CVBS0
VCOM0
AV
D
D
_M
I
PWM0
SAR2
SAR0
GND
SPI_SCZ
SPI_SCK
GND
SAR3
SAR1
VDDC
SPI_SDO
SPI_SDI
USB20_DM
AVDD_USB
USB20_REXT
MVREF
MCLKE
MCLK
MCLKZ
DQM1
DQS1
MDATA[15]
MDATA[11]
MDATA[10]
AVDD_MI
MDATA[3]
MDATA[2]
GND
MDATA[1]
MDATA[0]
AVDD_MI
DQS0
DQM0
INT
DDCA_SCL
DDCA_SDA
DDCR_SCL
DDCR_SDA
PWM1
GPIOR[0]
G
PI
O
D
[3
]
G
PI
O
D
[5
]
G
PI
O
D
[7
]
G
PI
O
D
[4
]
G
PI
O
D
[6
]
VD
D
P
AV
D
D
_M
IP
LL
GND_RXV
GND
USB20_DP
VDDP
GND
IRIN
VDDP
USB_DM
USB_VBUS
USB_DP
USB_CID
GPIOB[0]
GPIOB[1]
R
X1
P
G
N
D
XIN
MDATA[9]
MDATA[8]
AVDD_MI
MDATA[7]
MDATA[6]
MDATA[5]
MDATA[4]
MDATA[14]
MDATA[13]
MDATA[12]
AVDD_MI
GPIOL[2]
GPIOL[3]
A
D
[0
]
A
D
[1
]
A
D
[2
]
A
D
[3
]
G
N
D
VD
D
P
LV
B
0M
LV
B
0P
LV
B
1M
LV
B
1P
LV
B
2M
LV
B
2P
LV
B
CK
M
LV
B
CK
P
LV
B
3M
LV
B
3P
LV
B
4M
AVDD_MI
G
N
D
V
D
D
P
LV
A
0M
LV
A
0P
LV
A
1M
LV
A
1P
LV
A
2M
LV
A
2P
LV
A
C
KM
LV
A
C
KP
LV
A
3M
LV
A
3P
LV
A
4M
LV
A
4P
V
D
D
C
G
N
D
H
W
R
ES
ET
G
PI
O
E[
2]
G
PI
O
E[
0]
G
PI
O
E[
1]
G
PI
O
E[
3]
Mstar Confidential
for TCL
Internal Use Only