DGND
T
DGND
DGND
DGND
DGND
DGND
DGND
DGND
T
T
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
T
DGND
T
DGND
DGND
DGND
DGND
DGND
DGND
T
DGND
DGND
DGND
DGND
DGND
.............
4-14-2009_15:30
...........
...
...
...
...
DD-MM
DD-MM
DD-MM
DD-MM
...
...
...
...
...
...
...
...
...
...
...
...
DD-MM-YY
......
ADDRESS1
ADDRESS2
ADDRESS3
TELEPHONE
NAME
Last modif
DESCRIPTION
DATE
DESIGNATION
DRAWN
CHECKED
ON:
BY:
BY:
ON:
PAGE:
OF :
1
2
3
4
5
6
7
8
9
10
11
12
H
G
F
E
D
C
B
A
12
11
10
9
8
7
6
5
4
3
2
1
THIS DRAWING CANNOT BE COMMUNICATED TO UNAUTHORIZED PERSONS COPIED UNLES S PERMITTED IN WRITING
FORMAT DIN A1
H
G
F
E
D
C
A
Index-Lab
TCLNO:
SBU :
Last saved :
TCL
DGND
T
DGND
T
T
DGND
NC6
DQ0
DQ1
DQ2
DQ3
LDQSP
LDQSN
DQ4
DQ5
DQ6
DQ7
LDM
CKE
CKP
CKN
ODT
DQ8
DQ9
DQ10
DQ11
UDQSP
UDQSN
DQ12
DQ13
DQ14
DQ15
UDM
WEN
CASN
RASN
CSN
NC1
BA1
BA0
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
VDDQ
VSSQ
VDD
VSS
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VSS1
VSS2
VSS3
VSS4
VDD1
VDD2
VDD3
VDD4
VDDDL
NC4
NC3
NC2
VSSDL
VREF
NC5
T
T
T
T
DGND
DI
CLK
NC
VCC
VSS
WP
CS
DGND
DGND
T
DGND
T
T
T
T
T
T
DGND
DGND
SDA
SCL
WC
VCC
VSS
E2/NC
E1/NC
E0/NC
HWRESET
HOTPLUGA
RXACKN
RXACKP
RXA0N
RXA0P
AVDD_33A
RXA1N
RXA1P
DDCDA_DA
RXA2N
RXA2P
DDCDA_CK
ARC
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
VDDC
HSYNC0
BIN0P
SOGIN0
GIN0P
GIN0M
RIN0P
VSYNC0
AVDD_126
AVDD_25
BIN1P
SOGIN1
GIN1P
GIN1M
RIN1P
AVDD_33B
CVBS4
CVBS3
CVBS2
CVBS1
CVBS0
VCOM
CVBSOUT0
AUL0
AUR0
AUL1
AUR1
GND1
AUVRP
AUVAG
AVDD_AU25
AUL2
AUR2
AUL3
AUR3
AUL4
AUR4
AVDD_AU33
AUOUTL1
AUOUTR1
AUOUTL0
AUOUTR0
NC10
NC11
NC12
XIN
XOUT
AVDD_DMPLL
AVDD_REF
PGA_COM
VIFM
VIFP
AVDD_PGA
SIFP
SIFM
TAGC
I2S_OUT_WS
I2S_OUT_SD
GPIO24
GPIO25
SPDIFI
SPDIFO
VDDC1
VDDP1
GPIO28
I2S_OUT_MCK
I2S_OUT_BCK
GPIO36
GPIO37
GPIO38
USB1_DM
USB1_DP
PWM2
NC13
LVA4P
LVA4M
LVA3P
LVA3M
LVACKP
LVACKM
LVA2P
LVA2M
LVA1P
LVA1M
AVDD_MOD1
LVA0P
LVA0M
LVB4P
LVB4M
LVB3P
LVB3M
LVBCKP
LVBCKM
LVB2P
LVB2M
LVB1P
LVB1M
LVB0P
LVB0M
VDDC2
AVDD_MOD2
AVDD_LPLL
I2S_IN_WS
I2S_IN_SD
I2S_IN_BCK
I2S_OUT_MUTE
VDDP2
PWM0
PWM1
VDDC3
MADR[12]
MADR[9]
MADR[7]
MADR[5]
MADR[3]
MADR[10]
MADR[1]
BADR[2]
AVDD_DDR1
BADR[0]
BADR[1]
MCLKE
WEZ
MDATA[4]
AVDD_DDR2
MDATA[3]
MDATA[1]
MDATA[6]
MDATA[11]
AVDD_DDR3
MDATA[12]
MDATA[9]
MDATA[14]
DQMU
DQML
AVDD_DDR4
DQSL
DQSLZ
DVDD_DDR
AVDD_MEMPLL
DQSU
DQSUZ
MDATA[15]
MDATA[8]
AVDD_DDR5
MDATA[10]
MDATA[13]
MDATA[7]
MDATA[0]
MVREF
MDATA[2]
AVDD_DDR6
MDATA[5]
MCLK
AVDD_DDR7
MCLKZ
ODT
RASZ
CASZ
MADR[0]
MADR[2]
AVDD_DDR8
MADR[4]
MADR[6]
MADR[8]
MADR[11]
MADR[13]
VDDC4
DDCR_DA
VDDP3
DDCR_CK
USB0_DM
USB0_DP
AVDD_ALIVE
BYPASS
GND3
SCK
SDI
SDO
SCZ
SAR0
SAR1
SAR2
GPIO10
DDCA_CK
DDCA_DA
GPIO6
GPIO7
GPIO8
GPIO9
IRIN
CEC
E-PAD
GND2
Data & Addr
PM
UART SARx3
SPI
I2CM
USB0
DDR2
CVBSx5
Audio-Outx3
VIF & SIF
I2S Out & GPIO
Audio-Inx5
HDMIB
HDMIA
RGBx2
USB2
10Bit
LVDSx2
DGND
T
T
T
T
(6)
NC
NC
(1)
(1)
(1)
(4)
(3)
CORE POWER
FORMAT
CLOSE TO IC
CLOSE TO SOC POWER PIN
CLOSE TO DDR POWER PIN
(3)
(3)
(3)
(3)
(4)
(4)
(2)
(3)
(3)
(3)
(2)
(4)
(1)
(1)
Chip Config
Near IC PIN
(3)
(3)
(3)
(3)
(3)
(1)
(1)
(1)
Near IC PIN
AMP_MUTE
SDA2
SCL2
ROTATE
FORMAT
+3V3
MIC_L_IN
MIC_R_IN
L509 220R
R534 1K
1%
0.1U
C512
1%
1K
R533
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
73
74
75
76
77
78
79
80
81
82
83
84
85
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
196
197
198
199
200
201
202
203
204
205
206
208
209
210
211
212
213
214
215
216
217
195
U500
MST6M182VS
5
6
7
8
4
3
2
1
U503
M24C64
C504
0.1U
E2P_VCC
EEPROM-WP
GND_SPI
SPI_CZ1
SPI_SDO
VCC_SPI
WP
R505
10K
C507
33P
33P
C506
X24M
24M
C581
2U2
R546
100R
R545
100R
R547
100R
R527
NC/
100R
NC/
100R
R525
NC/
0.047U
C582
47P
C580
C579
47P
C578
0.1U
C576
0.1U
12V
C509
0.1U
C552
10U
1M
R541
1M
R501
R502
4K7
C500
1U
R555
100R
PANEL_ON
KEY_IN
LIGHTSENSOR_OUT
LED_OUT
IR_IN
BL_ON_OUT
LOGO_OUT
_IN
TU1_IF-_IN
AVOUT1_R_OUT
AVOUT1_R_OUT
AVOUT1_L_OUT
AVOUT1_L_OUT
AV1_R_IN
AV1_R_IN
AV1_L_IN
AV1_L_IN
HD1_SOG_IN
HD1_SOG_IN
HD1_PB_IN
HD1_PB_IN
AV1_V_IN
AV1_V_IN
AV2_V_IN
AV2_V_IN
CVBS_OUT
CVBS_OUT
HD1_L_IN
HD1_L_IN
HD1_R_IN
HD1_R_IN
C537
2U2
0.022U
C516
R548
4K7
68R
R553
R542
4K7
C575
10U
C574
10U
C573
0.1U
68R
R532
0.047U
C510
0.047U
C515
4K7
R519
R521
100R
100R
C508
2U2
R524
100R 1%
100R
R523
1%
C511
0.01U
C536
0.1U
0.1U
C535
0.1U
C534
C533
0.1U
0.1U
C532
C530
0.1U
0.1U
C529
0.1U
C528
C527
0.1U
C526
0.1U
0.1U
C525
C524
0.1U
0.1U
C523
0.1U
C522
C521
0.1U
C520
2U2
0.1U
C545
C544
0.1U
C543
0.1U
0.1U
C542
C541
0.1U
0.1U
C540
0.1U
C539
0.1U
C538
C551
0.1U
0.1U
C550
0.1U
C549
C548
0.1U
0.1U
C547
C546
2U2
C555
0.1U
C554
0.1U
0.1U
C553
C556
0.1U
C568
2U2
C569
0.1U
C570
0.1U
C571
0.1U
C572
0.1U
C557
2U2
C558
0.1U
C559
0.1U
0.1U
C560
C561
0.1U
C562
0.1U
C567
0.1U
C563
2U2
C564
0.1U
0.1U
C565
0.1U
C566
C505
22P
0.1U
C503
C501
10U
R500
8
3
1
2
7
4
5
22R
RP500
C502
1000P
R503
1K
R552
100K
5
6
7
8
4
3
1
U502
EN25Q32A
R554
10K
R537
10K
4K7
R551
R550
4K7
4K7
R549
R544
4K7
R543
4K7
R507
4K7
1K
R504
10K
R506
USB1_D-_IN
120R
L510
120R
MCU_RESET
GND501
UART_TX UART_RX
VGA_BLU_IN
VGA_SOG_IN
VGA_SOG_IN
VGA_GRN_IN
VGA_GRN_IN
VGA_RED_IN
VGA_RED_IN
H
H
GIN2M
HD1_PR_IN
AUVRM
M_SCL
E2
F7
E8
K2
J8
K8
K9
K3
L7
K7
L8
L1
L3
L2
R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8
A9
A7
A1
A3
B2
B8
D2
D8
E7
F2
F8
H2
H8
C1
C3
C7
C9
E9
G1
G3
G7
G9
E3
J3
N1
P9
E1
J9
M9
R1
J1
R8
R3
R7
J7
J2
A2
U501
K4T51163QI
VGA_VS_IN
VGA_HS_IN
VGA_BLU_IN
L505
L508
120R
L507
120R
120R
L504
120R
220R
220R
C531
0.1U
1
3
2
D500
0BAV99
0R
R530
4K7
R518
1
2
4
6
8
22
24
26
3
5
7
21
23
25
40
39
P500
1
2
3
4
P501
B
E
C
BT3906
Q500
GIN0M
_IN
SDA DIM_OUT
SCL
+3_3VSTB
M_SDA
A_MDATA11
A_MDATA6
A_MDATA1
A_MDATA3
SPDIF_OUT
DVDD_NODIE_1.2V
A_MDATA7
A_MDATA6
A_MDATA5
A_MDATA4
A-MVREF
1V8-DDR2
AVDD_DMPLL
AUVAG
AUVRP
SYNC
SPI_SDI
SPI_SCK
68R
R531
TUNER_5V
AVDD_DDR_1V8
R508
1K
R509
10K
Summary of Contents for L32D3200
Page 38: ......