TCL CSTM E18 V1, Service Manual

Page: 26 / 63

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
T
OUT
FAULT
ILIM
EN GND IN
SPI-CLE SPI-DATA SPI-CLK PVR_TS_DATA1 PVR_TS_DATA0 PVR_TS_SYNC PVR_TS_VAL PVR_TS_CLK CI_TS_DATA0 CI_TS_SYNC CI_TS_VAL CI_TS_CLK DVSS_1 DVDD33_1 DEMOD_TS_SYNC DEMOD_TS_VAL DEMOD_TS_CLK DEMOD_TS_DATA0 AVSS33_1 TP AVSS33_2
AVSS33_3 AVDD33_2
AVDD33_1
IFPGA_INN
AVDD12_2
DVSS_2
TUNER_DATA
RF_AGC
S2_TS_SYNC
S2_TS_DATA0
DVDD33_2
MT5135_RST_B DVDD10_1 AVDD12_1
EXT_CLKSEL
S2_TS_DATA3
S2_TS_DATA5
S2_TS_DATA7
CD1_
D4
D5
D6
D15
IF_AGC
DVDD33
A10 OE_
IOWR_
A17
DVDD10_3
A13
S2_TS_DATA2
A14
DVDD33_3
ADIN0 TN AVDD33 XTALI XTALO
IORD_
AVSS12
IFPGA_INP
AVDD33_3
WE_
A21
READY
D7
DVDD10_2
TUNER_CLK
S2_TS_CLK
S2_TS_VAL
DVSS_3
S2_TS_DATA1
S2_TS_DATA4
D3
S2_TS_DATA6
CHIP_CTRL
D11
D12
D13 D14
DVSS_5
CE1_
DVSS_4
VS1_
A11
A9 A8
DVSS_6
A18 A19 A20
A0
D8
D0
A22 A23
A24
A12
A15
A25
A7
VS2_
A16
BVD2
A1
CMCIA_RESET
A5
WAIT_
A2
BVD1
A4
DVDD33_4
DVSS_7
A3
REG_
DVSS_8
DVDD10_4
D9
D1
D10
D2
CD2_
CI_INT
DVSS_9
DVDD33_5
A6
GND
1
S3
S2
S1
S0
CLOSE TO MT8295
S0 S1 S2 S3
XX
X
0 1
0 1
1 0
1 1
NORMAL
SPI AS IIC
down:signle end
up:differential
CLOSE TO CI CONNECTOR
DVBS2 AS IIC
CLOSE TO MT530X
MT5315
CLOSE TO MT5135
close TO MT5315
CLOSE TO PCMCIA
CLOSE TO MT5315
C643 NC/10P
C636 NC/10P TS_VALID_IN
C635 NC/10P
C634 NC/10P
L608
NC/120R
L602
NC/120R
L601
NC/120R
L607
NC/120R
R645
NC/33R
NC/33R
R628
NC/33R
R629 R644
NC/33R
NC/0R
R637
R636
NC/0R NC/0R
R635
R634
NC/0R
NC/10K
R602
C605
NC/27P NC/27P
C606
X600 NC/27M
R612
NC/4K7
R622
NC/0R
NC/0R
R641
R642
NC/0R
R643
NC/0R
5 1 2 3 4 6 7 8 9 10 11 13 14 15 12 22 21 20 19 18 17 16 34 33 32 31 30 29 28 27 26 25 24 23
67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 41 40 39 38 37 36 35 68 42
P600
C620
NC/10P
C619
NC/10P
R639
NC/0R
NC/0R
R630
C645
NC/10P
NC/47R
R668
NC/22R
R666
NC/22R
R665
NC/22R
R664
NC/22R
R663
NC/22R
R662
NC/22R
R661
NC/22R
R660
NC/22R
R659
NC/22R
R658
NC/22R
R657
C609
NC/10P
NC/47R
R667
NC/22R
R631
NC/22R
R648
NC/22R
R649
NC/22R
R650
NC/22R
R651
NC/22R
R652
NC/22R
R653
NC/22R
R654
NC/22R
R655
NC/22R
R656
1 2 3 4 5 6 7 8 9
10 11 12 13 14 16 17 18 15 24 26 28 30 32 22
35
37
39
41
44
46
48
50
19 20 21
33
53
55
57
59
62
64
66 69
43
71 73 75 78 80 83 85
52
87 89
23 25 27 29 31
76
34
36
38
91 92 93 68
40
42
45
47
49
51
54
60
56
58
61
63
65 67 82 70 72 74 77 79 81 90 84 86 88
118
119
120
94 96
98
99
97
100
101
102
95
115
116
104
105
106
114
117
107
110
109
108
111
112
113
121
122
123
124
125
126
127
128
103
U600
NC/MT5135AE
NC/10K
R605
NC/10K R626
R633 NC/10K
C622
NC/0.1U
C623 NC/0.1U
NC/10K R632
NC/10K R627
R624 NC/10K
L604
NC/600R
C601
NC/10U
C607
NC/1U
C631 NC/0.1U
C632 NC/0.1U
C627 NC/0.1U
C628 NC/0.1U
C629 NC/0.1U
L605
NC/600R
C637
NC/0.1U
C602
NC/10U
C638
NC/0.1U
C611
NC/0.1U
C612
NC/0.1U
6 4 5
3 2 1
U601
NC/TPS2550
L606
NC/60R
C604
NC/100U
6V3
C626 NC/0.1U
CI_GPIO8
R600
NC/0R
C610
NC/0.1U
C640 NC/0.1U
C613 NC/0.1U
C639 NC/0.1U
C608
NC/1U
6V3
NC/47U
C644
L600
NC/600R
C642
NC/0.1U
C641
NC/0.1U
C603
NC/10U
L603
NC/600R
M_CI_INDATA0
GND
TS1INDATA0
CI_DV33
TS1INDATA1
CI_CD1#
CI_D3
M_CI_OUTDATA3
NC/10K
R603
NC/10K
R609
NC/10K
R607
CI_VCC
R617
NC/100R
R613
NC/10K
R618
NC/100R
C630 NC/0.1U
NC/10K
R619
R620
NC/24K
R614
NC/100K
+5V
C625
NC/0.1U
C624
NC/0.1U
R621
NC/10K
C600
NC/1U
NC/10P
C633
C617
NC/10P
C618
NC/10P
C615
NC/10P
C616
NC/10P
R606
NC/10K
R608
NC/10K
R610
NC/10K
R604
NC/10K
NC/10K
R616
R623
NC/10K
CI_GPIO9 CI_GPIO8
M_CI_INDATA2
CI_D6
CI_CE1##
CI_DV33
M_CI_INDATA1
CI_A13
CI_A8
M_CI_OUTCLK
M_CI_OUTDATA7
M_CI_OUTDATA6 M_CI_OUTDATA5
M_CI_OUTDATA4 M_CI_OUTDATA3
M_CI_OUTDATA2 M_CI_OUTDATA1 M_CI_OUTDATA0
M_CI_OUTSYNC
M_CI_OUTVALID
M_CI_INCLK
M_CI_INDATA7 M_CI_INDATA6 M_CI_INDATA5 M_CI_INDATA4
M_CI_INDATA3 M_CI_INDATA2 M_CI_INDATA1 M_CI_INDATA0
M_CI_INSYNC
M_CI_INVALID
CI_INSYNC
CI_INVALID
CI_INCLK
CI_OUTCLK
M_CI_INCLK
CI_OUTCLK
CI_OUTSYNC
CI_OUTSYNC
CI_OUTVALID CI_OUTDATA7 CI_OUTDATA6 CI_OUTDATA5 CI_OUTDATA4 CI_OUTDATA3
CI_OUTDATA2
CI_OUTDATA1 CI_OUTDATA0
CI_INDATA7 CI_INDATA6
CI_INDATA5
CI_INDATA0
CI_INDATA1 CI_INDATA2 CI_INDATA4
CI_DV33
CI_DV33
CI_SPI_DATA CI_SPI_CLE
CI_SPI_CLK
VCCK
AVDD3V3
AVDD3V3
R611
NC/1M
CI_DV10
CI_DV33
CI_DV10
CI_AV12
CI_AV33
CI_DV33
CI_DV33
CI_DV33
CI_AV33
CI_AV33
CI_AV12
CI_DV10
CI_AV12
AVDD1V2
CI_DV10
CI_AV33
CI_AV33
R646 NC/10K
R638
4K7
CI_DV33
CI_DV33
CI_AV33
CI_VCC
CI_DV33
10K R625
CI_VCC
CI_VCC
CI_VCC
CI_DV10
CI_TS_DATAO
CI_TS_CKO
CI_TS_VALIDO
CI_TS_SYNCO
CI_OE##
CI_WE#
CI_CE1#
CI_CD2#
CI_CD1#
CI_IOWR# CI_INSYNC CI_INDATA0 CI_OUTVALID
CI_A11
CI_INDATA5
CI_D4
CI_CD1#
CI_A8
CI_CD2#
CI_D5 CI_A0
CI_IORD##
CI_IREQ#
CI_OUTDATA3 CI_WAIT# CI_INDATA4
CI_D0 CI_D6 CI_INCLK CI_A13
CI_INDATA7 CI_OUTDATA7 CI_VS1#
CI_D3 CI_D7
CI_CE2#
CI_A12
CI_INDATA2
CI_A14 CI_A3
CI_IOWR##
CI_OUTDATA0 CI_INDATA6 CI_OUTDATA4
CI_A4
CI_OUTDATA6 CI_OUTDATA2 CI_RESET
CI_INVALID
CI_INDATA3 CI_OUTDATA1
CI_A6 CI_A7
CI_OUTDATA5 CI_INDATA1
CI_A9 CI_A5
CI_IORD#
CI_VCC
CI_REG#
CI_OE#
CI_WE##
CI_A10
CI_VCC
CI_VCC CI_VCC
CI_A2 CI_A1 CI_D1
CI_VS1#
CI_CE2#
CI_WAIT#
CI_IREQ#
CI_OUTCLK
CI_OUTDATA6 CI_OUTDATA5
CHIP_CTRL
CI_OUTDATA3
CI_SPI_CLK
SPI_CLK
SPI_DATA
SPI_CLE
CI_SPI_CLE
CI_SPI_DATA
CI_INT# M_CI_INVALID
M_CI_INSYNC
CI_INT
TS_CLK_IN
TS_D0_IN
CI_TS_DATAO
TS_SYNC_IN
CI_TS_SYNCO
GPIO_10
CI_TS_VALIDO
CI_TS_CKO
CI_A6
CI_INT
CI_CD2#
CI_D2
M_CI_OUTDATA2
CI_D1
M_CI_OUTDATA1
CI_REG#
CI_A3
CI_A4
M_CI_OUTSYNC
CI_A2
CI_WAIT#
CI_A5
CI_RESET
CI_A1
M_CI_OUTVALID
M_CI_INVALID
M_CI_OUTCLK
CI_A7
M_CI_INDATA7
CI_A12
M_CI_INDATA6
M_CI_INDATA5 M_CI_INDATA4
CI_D0
M_CI_OUTDATA0
CI_A0
CI_A9 CI_A11
CI_VS1#
CI_CE1##
M_CI_OUTDATA6 M_CI_OUTDATA5
M_CI_OUTDATA4
CHIP_CTRL
TS1INDATA6
TS1INDATA4
TS1VALID
TS1CLK
TUNER_SCL
CI_D7
CI_IREQ#
M_CI_INDATA3
CI_WE##
5
CI_IORD##
CI_A14
TS1INDATA2
M_CI_INSYNC
CI_IOWR##
CI_OE##
CI_A10
D_IF_AGC
M_CI_OUTDATA7
CI_D5
CI_D4
TS1INDATA7
TS1INDATA5
TS1INDATA3
TS1SYNC
D_RF_AGC
TUNER_SDA
5135_FAT-
CI_XTALO
CI_XTALI
CI_RESET#
CI_GPIO9
CI_INDATA3
CI_D2