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A

3

2

1

F

E

D

C

B

8

7

6

5

5

4

3

2

1

THIS DRAWING CANNOT BE COMMUNICATED TO UNAUTHORIZED PERSONS COPIED UNLES S PERMITTED IN WRITING

F

E

D

C

B

A

4

6

7

8

FORMAT DIN A2

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

RDQM0

RDQS0

RDQS0#

RDQ0
RDQ1
RDQ2
RDQ3
RDQ4
RDQ5
RDQ6
RDQ7

RDQM1

RDQS1

RDQS1#

RDQ8
RDQ9

RDQ10
RDQ11
RDQ12
RDQ13
RDQ14
RDQ15

RDQM2

RDQS2

RDQS2#

RDQ16
RDQ17
RDQ18
RDQ19
RDQ20
RDQ21
RDQ22
RDQ23

RDQM3

RDQS3

RDQS3#

RDQ24
RDQ25
RDQ26
RDQ27
RDQ28
RDQ29
RDQ30
RDQ31

AVDD33_DDR
AVDD12_DDR

AVSS12_DDR

RA0
RA1
RA2
RA3
RA4
RA5
RA6
RA7
RA8
RA9
RA10
RA11
RA12
RA13
RA14
RA15
RBA0
RBA1
RBA2
RCS#
RCSD#
RRAS#
RCAS#
RWE#
RODT
RCKE
RRESET
RCLK0
RCLK0#
DDRVREF_A1
DDRVREF_A2
ARTP
ARTN
MEMTP
MEMTN
TP_HPCPLL
TN_HPCPLL

DDRV
DDRV1
DDRV2
DDRV3
DDRV4
DDRV5
DDRV6
DDRV7
DDRV8
DDRV9

DDRVA

DDRV10
DDRV11
DDRV12
DDRV13
DDRV14

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

DQSU

/DQSU

DMU

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQSL

/DQSL

DML

BA0
BA1
BA2

/CS
/RAS
/CAS
/WE

CK

/CK

CKE

ODT

/RESET

VREFCA

VREFDQ

ZQ

VDDQ

VDDQ1

VDDQ2

VDDQ3

VDDQ4

VDDQ5

VDDQ6

VDDQ7

VDDQ8

VSSQ

VSSQ1

VSSQ2

VSSQ3

VSSQ4

VSSQ5

VSSQ6

VSSQ7

VSSQ8

VDD

VDD1

VDD2

VDD3

VDD4

VDD5

VDD6

VDD7

VDD8

VSS

VSS1

VSS2

VSS3

VSS4

VSS5

VSS6

VSS7

VSS8

VSS9

VSS10

NC1
NC2
NC3
NC4
NC5
NC6
NC7

VSS11

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

DQSU

/DQSU

DMU

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQSL

/DQSL

DML

BA0
BA1
BA2

/CS
/RAS
/CAS
/WE

CK

/CK

CKE

ODT

/RESET

VREFCA

VREFDQ

ZQ

VDDQ

VDDQ1

VDDQ2

VDDQ3

VDDQ4

VDDQ5

VDDQ6

VDDQ7

VDDQ8

VSSQ

VSSQ1

VSSQ2

VSSQ3

VSSQ4

VSSQ5

VSSQ6

VSSQ7

VSSQ8

VDD

VDD1

VDD2

VDD3

VDD4

VDD5

VDD6

VDD7

VDD8

VSS

VSS1

VSS2

VSS3

VSS4

VSS5

VSS6

VSS7

VSS8

VSS9

VSS10

NC1
NC2
NC3
NC4
NC5
NC6
NC7

VSS11

Near DDR

Near U001

Differential Clock

Support Asymmetry/Symmetry DRAM

Change PN

Bottom SIDE

Near DRAM

TOP SIDE

Bottom SIDE

TOP SIDE

DDR REF Volt

SOC-DDR

DDR

Change PN

For MCM Dram VREF

U001 Bottom SIDE

Close to U201

K3

K7

L2

G3

B7

J3

T2

L3

N3

P7

L7

R7
N7

P3

N2

P8
P2

R8
R2

T8

R3

M2

N8

M3

J7

K9

E7

D3

E3
F7
F2
F8
H3
H8
G2
H7

F3

C7

D7
C3
C8
C2
A7
A2
B8
A3

J1
J9

L1
L9

M7

T3
T7

K1

B2

D9

G7

K2

K8

N1

N9

R1

R9

A1

A8

C1

C9

D2

E9

F1

H2

H9

M8

H1

A9

E1

T9

B3

G8

J2

J8

M1

M9

P1

P9

T1

B9

B1

D1

D8

E2

E8

F9

G1

G9

L8

U302

H5TQ4G63AFR

K3

K7

L2

G3

B7

J3

T2

L3

N3

P7

L7

R7
N7

P3

N2

P8
P2

R8
R2

T8

R3

M2

N8

M3

J7

K9

E7

D3

E3
F7
F2
F8
H3
H8
G2
H7

F3

C7

D7
C3
C8
C2
A7
A2
B8
A3

J1
J9

L1
L9

M7

T3
T7

K1

B2

D9

G7

K2

K8

N1

N9

R1

R9

A1

A8

C1

C9

D2

E9

F1

H2

H9

M8

H1

A9

E1

T9

B3

G8

J2

J8

M1

M9

P1

P9

T1

B9

B1

D1

D8

E2

E8

F9

G1

G9

L8

U301

H5TQ4G63CFR-RDC

AA3
Y2
Y1
U3
AE2
T3
AE1
R2
AF2
R1
AF1
W2
AB3
AB2
AD2
U1
AD3
U2
AC3
V1
AC1
V2
AF8
AG7
AH7
AG3
AG12
AF3
AH12
AG2
AG13
AH2
AH13
AG6
AF9
AG9
AF12
AH4
AF11
AG4
AG10
AF5
AH10
AF6

U4
Y15

W15

AB4

AC9

AE3
AE6

AD9

AE4

AC11

AD5

AE9
AE5
AE7

AD11

AE12

AC5

AE10
AE11

AD7

AE8

AC7

V4

W4

AA5
AA6

AC4

W5
W6

U6

AA4

Y4

U5

AE13

W9
W8

Y8
Y9

AC20
AD20

R4

T4

R5

T5

R6

T6

R7

T7

R8

V8

T8

R9

T9

U9

V9

AB12

U201

MT5507

C317

4U7

22U

C316

DDR_1V5

C325

1U

0.1U

C313

0.1U

C323

C240

0.1U

C238 1U

R235

0R

2_RCSD

1_RCS

R231

48R7

R230

120R

R308

47R

R307

47R

C345

0.1U

C309

0.1U

C342

0.1U

R306

1K

R305

1K

R304

1K

R303

1K

1K

R301

NC/

0.1U

C239

RDQS0B

1_A1

2_A12

2_A6

RA15

2_A8

2_A14

2_A4

2_A1

RA4

RA1

2_BA1

2_A10

2_BA0

2_BA2

RBA1

RBA0

5

4

7

2

1

3

6

8

R318

22R

2_A3

2_A13

RA3

RA9

RA13

RRESET

RRESET

2_A7

2_A2

2_A5

2_A0

RA7

RA2

RA5

RA0

2_CAS#

RA15

RA12

RA11

RA6

1_A15

RA8

RA14

RA4

1_A14

1_A4

RA1

RBA1

RA10

RBA0

RBA2

1_A10

1_BA2

RA3

RA13

1_A3

RA7

RWE

RODT

1_CAS#

RRAS

1_RAS#

0.1U

C344

DDR_1V5

DDR_1V5

DDR_1V5

DDR_1V5

DDR_1V5

DDR_1V5

DDR_1V5

DDR_1V5

A_VREFCA1

DDRVREF_A1

0.1U

C338

0.1U

C337

C333

0.1U

0.1U

C332

1U

C331

22U

C327

0.1U

C324

0.1U

C322

C321

0.1U

NC/

0.1U

C319

0.1U

C318

0.1U

C315

10U

C308

C307

0.1U

0.1U

C305

1U

C302

0.1U

C303

R310

240R

1U

C306

RDQS2

C339

1U

DDRVREF_A2

DDRVREF_A2

MCLK0B

1K

R302

NC/

RCLK0B

RCAS

RCS

RBA1

5

4

7

2

1

3

6

8

R322

22R

10U

C301

22U

C340

NC/

0.1U

C336

0.1U

C335

0.1U

C334

0.1U

C329

C312

1U

0.1U

C320

22U

C310

C314

0.1U

0.1U

C341

5

4

7

2

1

3

6

8

R313

22R

10U

C311

5

4

7

2

1

3

6

8

R314

22R

5

4

7

2

1

3

6

8

R316

22R

5

4

7

2

1

3

6

8

R315

22R

5

4

7

2

1

3

6

8

R312

22R

5

4

7

2

1

3

6

8

R311

22R

R309

240R

5

4

7

2

1

3

6

8

R319

22R

5

4

7

2

1

3

6

8

R320

22R

5

4

7

2

1

3

6

8

R321

22R

5

4

7

2

1

3

6

8

R317

22R

0.1U

C343

0.1U

C326

10U

C328

0.1U

C330

0.1U

C304

RRESET

1_A12

1_A11

1_A6

1_A8

1_BA1

1_BA0

1_A9

1_A13

RRESET

1_A7

1_A2

1_A5

1_A0

1_WE#

RODT

RA5

RA9

RRESET

RA2

RA0

RCAS

RA12

RA11

RA6

RA8

RA14

RA10

RBA2

RWE

RODT

RCAS

RRAS

2_A15

2_A11

2_A9

2_WE#

RODT

2_RAS#

A_VREFCA1

RODT

1_A14

1_A13

1_A15

RDQ15

RDQ14

RDQ13

RDQ12

RDQ11

RDQ10

RDQ9

RDQ8

RDQS1

RDQS0

RDQ7

RDQ6

RDQ5

RDQ4

RDQ3

RDQ2

RDQ1

RDQ0

RDQM1

RDQM0

RCKE

RCLK0

1_BA2

1_BA1

1_BA0

1_WE#

RRESET

1_RAS#

RDQS1B

RDQS0B

1_RCS

RCLK0B

1_CAS#

DDRVREF_A1

A_VREFCA2

RODT

2_A14

2_A13

2_A15

RDQ31

RDQ30

RDQ29

RDQ28

RDQ27

RDQ26

RDQ25

RDQ24

RDQS3

RDQS2

RDQ23

RDQ22

RDQ21

RDQ20

RDQ19

RDQ18

RDQ17

RDQ16

RDQM3

RDQM2

RCKE

RCLK0

2_BA2

2_BA1

2_BA0

2_A9

2_A8

2_A7

2_A6

2_A5

2_A4

2_A3

2_A2

2_A12

2_A11

2_A10

2_A1

2_A0

2_WE#

RRESET

2_RAS#

RDQS3B

RDQS2B

2_RCSD

2_CAS#

DDRVREF_A2

RBA2

1_A9

1_A8

1_A7

1_A6

1_A5

1_A4

1_A3

1_A2

1_A12

1_A11

1_A10

1_A1

1_A0

RA3

RA2

RA1

RA0

RA9

RA8

RA7

RA6

RA5

RA4

RA12

RA11

RA10

RA15

RA14

RA13

RBA0

RCSD

RODT

RWE

RRAS

RCKE

MCLK0

RRESET

ARTN

ARTP

RDQ26

RDQ25

RDQ24

RDQS3B

RDQ31

RDQ30

RDQ29

RDQ28

RDQ27

RDQ0

RDQS0

RDQM0

RDQ4

RDQ3

RDQ2

RDQ1

RDQM1

RDQ7

RDQ6

RDQ5

RDQ9

RDQ8

RDQS1B

RDQS1

RDQ13

RDQ12

RDQ11

RDQ10

RDQM2

RDQ15

RDQ14

RDQS3

RDQ17

RDQ16

RDQS2B

RDQ21

RDQ20

RDQ19

RDQ18

RDQM3

RDQ23

RDQ22

A_VREFCA2

3V3

CORE_1V2

R234

100R

R233

0R

MCLK0B

MCLK0

RCLK0B

RCLK0

R232

0R

RCS

RCSD

Summary of Contents for 48D2700/MT56B-AP

Page 1: ...n 3 Alignment Procedure 4 Block diagram 5 Scheme Diagram 6 Troubleshooting SORGH GUDZLQJ This m anual i s t he l atest at t he t ime of pr inting and doe s not include the modification which may be ma...

Page 2: ...ectric shock to the person The exclamation point within an equilateral triangle is intended to alert the user to the presence of important operating and maintenance servicing instructions in the liter...

Page 3: ...impact of any kind Be particularly careful not to damage the picture tube surface 9 Unplug this television set from the wall outlet before cleaning Do not use liquid cleaners or aerosol cleaners Use...

Page 4: ...ng conductors location of antenna discharge unit connection to grounding electrode and requirements for the grounding electrode 15 2 Note to CATV system installer Only for the television set with CATV...

Page 5: ...durein youroperatinginstructions do not attempt any further adjustment Unplug the set and call your dealer or service technician 22 Whenever the television set is damaged or fails or a distinct change...

Page 6: ...ion Internet Link Panel Specification p Initial Setup Yes for user setting in TV first starting Viewing Angle H V 178 178 HDMI Auto Switch Auto Close Manual Life Time Typ 30 000hrs Channels Edit For C...

Page 7: ...ecast Showed in Homepage E Sticker as some function demo in Shop mode Miracast p E Manual Some general basic function introduction Connect Mobile phone to TV sets and control the TV like Remote using...

Page 8: ...Factory Test Alignment Specification For MT56 AP Series V1 0 1 TCL World Wide R D FPD CENTER Factory Test Alignment Specification V1 0 MT56 AP PREPARED BY FENG LIU DATE 2015 02 13 APPROVED BY DATE...

Page 9: ...Accessing Way 8 3 2 Design Menu 8 3 3 Other Menu 9 3 4 Service Menu 9 3 5 Param Setting Menu 10 4 Test Alignment 11 4 1 Pre Conditions and Power Supply Check 11 4 2 Project ID Modification 11 4 3 Func...

Page 10: ...ain Menu FMM is divided into Factory menu and Design menu Factory Menu covers all indispensable functions during manufacture such as White Balance Adjustment SHOP etc while Design Menu includes Servic...

Page 11: ...VGA IC Details Position Main program UF01 Support online upgrade Mboot UF01 Support online upgrade EEPROM U702 Note The software boot for U702 can be programed by Flash Tool exe Every set has its uni...

Page 12: ...ast item submenu Finally press 9 7 3 5 consecutively b When the Factory hotkey item of Factory Menu is enabled ON you can see the flashing Factory Captions Info on the lower left corner press Back but...

Page 13: ...ance ADC data Power On Mode STANDBY ON the set will power on after switching on power STANDBY the set will remain standby status after switching on power LAST the set will turn to the status in which...

Page 14: ...n Hotel Menu we also provide a great deal of useful functions for specific applications in hotel White Balance Name Default Description Source ATV Press RCU left right key to change the TV source Colo...

Page 15: ...u key exit the Factory menu Design Captions Information is the same to Factory Captions Info 3 2 Design Menu Design Menu Name Default Description Design Mode hotkey OFF Design Menu shortcut button swi...

Page 16: ...into test pattern and restarting TV is the only way to excit UartEnable OFF The switch of VGA serial port information The item must be disabled OFF after production DeviceID Show the device id of TV M...

Page 17: ...se shouldn t change the settings in the menu Param setting Menu Name Default Description Sound Setting Set sound mode balance sound scene etc Picture Curve Exclusively used by R D Picture Setting Set...

Page 18: ...he relevant block diagram and circuit diagram make sure that no serious issue or mistake can destroy the board For example the output of DC DC and LDO should not be shorted to ground Supply a suited v...

Page 19: ...s When the set restart automatically you have successfully changed project ID Here below is none exhaustive ProjectID table for reference MODEL ProjectID Panel Name L40S4690FS 001 LVF400NEAL 4 3 Funct...

Page 20: ...quirements rev v3 9 LAN Test A rough LAN test can be done by connecting Ethernet to TV s RJ45 and check that IP subnet mask DNS addresses which are visible on Home Settings Network Ethernet settings I...

Page 21: ...rn In Additional aging for White Balance alignment is no more necessary due to consistent picture performance with cloning usage This function is accessible by selecting Factory menu Warm up pressing...

Page 22: ...boot Connect the computer and mainboard VGA port by a serial port tool Serial connector definition VGA P303 Pin4 RXD VGA Pin11 TXD Open MTK Mboot software programming tool Flash Tool and set serial po...

Page 23: ...low screen Upgrade process takes about 3 5 minutes After updating the TV set will reset automatically 2 Online Upgrade Download the bin zip file V8 MT56551 LF1VXXX Zip to the root directory of your US...

Page 24: ...tlet using a network cable Note that the wall outlet is attached to a modem or router anywhere in your house Select Home Settings Network Ethernet Settings IP Settings then the TV will obtain IP addre...

Page 25: ...e chromaticity coordinate tolerance X Y X Y LCD cold 13000K 0 270 0 270 0 015 normal 10000K 0 280 0 290 warm 7500K 0 300 0 305 White balance adjustment takes the Normal color temperature of HDMI chann...

Page 26: ...rmal DDR_1V5 CI_VCC CORE_1V2 12V 5V 12V 5V CORE_1V2 DDR_1V5 5V 3V3_Normal 5V TU_3V3 5V 3V3_DEMO 5V 1V1_DEMO 3V3 1V8 12V 3V3SB 3V33B CORE_1V2 3V3 3V3 1V8 3V3 12V 3V3_DEMO 1V1_DEMO 3V3_Normal 1V8 5V MHL...

Page 27: ...22U D050 SR34 L050 3 3UH 0 1U C053 3 2 1 4 5 6 U002 AN_SY8291 C052 0 1U 2 2U C051 C050 2 2U 3V3SB 47K R903 NC R905 150K 1 2 3 4 5 P900 1 2 3 4 P901 12V_AMP L001 220R 12V 12V_M L901 600R C901 0 1U CA...

Page 28: ..._FAT TUNER_FAT TU_3V3 IF_AGC_T2 IF_AGC_T2 6 11 10 7 8 1 3 2 4 5 9 TU02 10 6 7 8 1 3 2 4 5 9 TU01 R151 47K R150 0R NC R149 0R X100 24M TU_3V3 TU_IFAGC R250 1K R251 10K IF_AGC R135 4K7 R134 4K7 R249 1K...

Page 29: ...V AUDIO OUT R338 120R 1 2 P904 F904 F903 F902 F901 1 2 D904 PESD5V0S1BL NC 2 1 D903 PESD5V0S1BL 2 1 D902 PESD5V0S1BL 2 1 PESD5V0S1BL D901 C916 0 1U C915 220P C914 470P C913 470P C912 150P NC C911 150P...

Page 30: ...36 0 1U C935 0 047U 10U C934 0 1U C933 B C E Q903 BT3904 E C B BT3904 Q902 B C E Q901 BT3904 E C B BT3904 Q900 R970 100K R969 75R R968 910R 47K R967 R966 47K 47K R965 47K R964 100R R963 100R R962 R961...

Page 31: ...reset time is 80ms When input is 12V reset vol 8 4V MTK Reset at low level Bottom SIDE SOC POWER SOC EMMC SOC CI SOC RESET SOC USB SOC Ethernet STRAPPING OPCTRL3 eMMC pins share pins w s NAND ICE moc...

Page 32: ...AG6 AF9 AG9 AF12 AH4 AF11 AG4 AG10 AF5 AH10 AF6 U4 Y15 W15 AB4 AC9 AE3 AE6 AD9 AE4 AC11 AD5 AE9 AE5 AE7 AD11 AE12 AC5 AE10 AE11 AD7 AE8 AC7 V4 W4 AA5 AA6 AC4 W5 W6 U6 AA4 Y4 U5 AE13 W9 W8 Y8 Y9 AC20 A...

Page 33: ...A 9 9 R333 4K7 47R R332 R331 47R R330 47R 47R R329 47R R328 R327 47R R326 47R 47R R325 47R R324 R323 47R W6 W5 K2 H3 H4 H5 J2 J3 J4 J5 J6 T5 H6 U5 U9 T10 N5 M6 AA3 AA5 Y4 W4 K6 K4 M7 P5 R10 U8 Y2 Y5 A...

Page 34: ...TA LRCIN SDA SCL RESET VSS RB VDDRB VDDLB LB GNDL NC2 VDDLA LA VDD SA0 MCLK BCLK 5 5 5 5 RED WHITE 5 5 1 5 7 7 Close to SOC AD82587D_12V 9 9 12V_AMP 22UH L604 22UH L603 L602 22UH 22UH L601 L600 120R 0...

Page 35: ...VDS Panel Power 4 LG_DIM_OUT are PWM port 5 DIM_SW_OUT is from DIM switch circuit 6 IIC option for panel 7 Default value in this diagram is for panel without IIC 8 DIM option for MCU 9 Define MCU port...

Page 36: ...3 4 CN802 FSW C774 100P B801 100P C807 1000P C830 B770 R832 10K NC Q770 A0D256 R785 0 33R EN 25V 470U C832 C851 47U 100V R824 0R FB C806 100P R853B 4 7K ZD851 33V R853A 4 7K ZD850 33V 12VOUT R823 0R...

Page 37: ...IIC bus Check the peripheral circuit of mail IC check solder of main IC check data fo NVM and reset it Check reset signal of main no switch on Check 3 3V 12V 24V of power supply Check PW Check DC DC p...

Page 38: ...IC check LVDS cable Check crystal frequence Check the peripheral circuit of mail IC updating SW reset NVM replace main IC Abnormal picture All signal source bad Individual signal source bad Check the...

Page 39: ...e function Abnormal sound Check all sound source Individual sound signal source Check the sound signal link to main IC Check the peripheral circuit of main IC SW Check the power of sound IC Check soun...

Page 40: ......

Page 41: ...n 3 Alignment Procedure 4 Block diagram 5 Scheme Diagram 6 Troubleshooting SORGH GUDZLQJ This m anual i s t he l atest at t he t ime of pr inting and doe s not include the modification which may be ma...

Page 42: ...ectric shock to the person The exclamation point within an equilateral triangle is intended to alert the user to the presence of important operating and maintenance servicing instructions in the liter...

Page 43: ...impact of any kind Be particularly careful not to damage the picture tube surface 9 Unplug this television set from the wall outlet before cleaning Do not use liquid cleaners or aerosol cleaners Use...

Page 44: ...ng conductors location of antenna discharge unit connection to grounding electrode and requirements for the grounding electrode 15 2 Note to CATV system installer Only for the television set with CATV...

Page 45: ...durein youroperatinginstructions do not attempt any further adjustment Unplug the set and call your dealer or service technician 22 Whenever the television set is damaged or fails or a distinct change...

Page 46: ...renamed Color 16 7 Million 8bit Input Settings For Input source device choice Refresh Rate 60Hz Sleep Timer Yes System Update Yes T Link CEC Yes Rearview Picture Input Method Smart TV IME MHL Yes Tele...

Page 47: ...mode E Manual Some general basic function introduction Connect Mobile phone to TV sets and control the TV like Remote using Phone Push media file in Phone to TV Display and Enjoy big screen picture q...

Page 48: ...Factory Test Alignment Specification For MT56 AP Series V1 0 1 TCL World Wide R D FPD CENTER Factory Test Alignment Specification V1 0 MT56 AP PREPARED BY FENG LIU DATE 2015 02 13 APPROVED BY DATE...

Page 49: ...Accessing Way 8 3 2 Design Menu 8 3 3 Other Menu 9 3 4 Service Menu 9 3 5 Param Setting Menu 10 4 Test Alignment 11 4 1 Pre Conditions and Power Supply Check 11 4 2 Project ID Modification 11 4 3 Func...

Page 50: ...ain Menu FMM is divided into Factory menu and Design menu Factory Menu covers all indispensable functions during manufacture such as White Balance Adjustment SHOP etc while Design Menu includes Servic...

Page 51: ...VGA IC Details Position Main program UF01 Support online upgrade Mboot UF01 Support online upgrade EEPROM U702 Note The software boot for U702 can be programed by Flash Tool exe Every set has its uni...

Page 52: ...ast item submenu Finally press 9 7 3 5 consecutively b When the Factory hotkey item of Factory Menu is enabled ON you can see the flashing Factory Captions Info on the lower left corner press Back but...

Page 53: ...ance ADC data Power On Mode STANDBY ON the set will power on after switching on power STANDBY the set will remain standby status after switching on power LAST the set will turn to the status in which...

Page 54: ...n Hotel Menu we also provide a great deal of useful functions for specific applications in hotel White Balance Name Default Description Source ATV Press RCU left right key to change the TV source Colo...

Page 55: ...u key exit the Factory menu Design Captions Information is the same to Factory Captions Info 3 2 Design Menu Design Menu Name Default Description Design Mode hotkey OFF Design Menu shortcut button swi...

Page 56: ...into test pattern and restarting TV is the only way to excit UartEnable OFF The switch of VGA serial port information The item must be disabled OFF after production DeviceID Show the device id of TV M...

Page 57: ...se shouldn t change the settings in the menu Param setting Menu Name Default Description Sound Setting Set sound mode balance sound scene etc Picture Curve Exclusively used by R D Picture Setting Set...

Page 58: ...he relevant block diagram and circuit diagram make sure that no serious issue or mistake can destroy the board For example the output of DC DC and LDO should not be shorted to ground Supply a suited v...

Page 59: ...s When the set restart automatically you have successfully changed project ID Here below is none exhaustive ProjectID table for reference MODEL ProjectID Panel Name L40S4690FS 001 LVF400NEAL 4 3 Funct...

Page 60: ...quirements rev v3 9 LAN Test A rough LAN test can be done by connecting Ethernet to TV s RJ45 and check that IP subnet mask DNS addresses which are visible on Home Settings Network Ethernet settings I...

Page 61: ...rn In Additional aging for White Balance alignment is no more necessary due to consistent picture performance with cloning usage This function is accessible by selecting Factory menu Warm up pressing...

Page 62: ...boot Connect the computer and mainboard VGA port by a serial port tool Serial connector definition VGA P303 Pin4 RXD VGA Pin11 TXD Open MTK Mboot software programming tool Flash Tool and set serial po...

Page 63: ...low screen Upgrade process takes about 3 5 minutes After updating the TV set will reset automatically 2 Online Upgrade Download the bin zip file V8 MT56551 LF1VXXX Zip to the root directory of your US...

Page 64: ...tlet using a network cable Note that the wall outlet is attached to a modem or router anywhere in your house Select Home Settings Network Ethernet Settings IP Settings then the TV will obtain IP addre...

Page 65: ...e chromaticity coordinate tolerance X Y X Y LCD cold 13000K 0 270 0 270 0 015 normal 10000K 0 280 0 290 warm 7500K 0 300 0 305 White balance adjustment takes the Normal color temperature of HDMI chann...

Page 66: ...rmal DDR_1V5 CI_VCC CORE_1V2 12V 5V 12V 5V CORE_1V2 DDR_1V5 5V 3V3_Normal 5V TU_3V3 5V 3V3_DEMO 5V 1V1_DEMO 3V3 1V8 12V 3V3SB 3V33B CORE_1V2 3V3 3V3 1V8 3V3 12V 3V3_DEMO 1V1_DEMO 3V3_Normal 1V8 5V MHL...

Page 67: ...22U D050 SR34 L050 3 3UH 0 1U C053 3 2 1 4 5 6 U002 AN_SY8291 C052 0 1U 2 2U C051 C050 2 2U 3V3SB 47K R903 NC R905 150K 1 2 3 4 5 P900 1 2 3 4 P901 12V_AMP L001 220R 12V 12V_M L901 600R C901 0 1U CA...

Page 68: ..._FAT TUNER_FAT TU_3V3 IF_AGC_T2 IF_AGC_T2 6 11 10 7 8 1 3 2 4 5 9 TU02 10 6 7 8 1 3 2 4 5 9 TU01 R151 47K R150 0R NC R149 0R X100 24M TU_3V3 TU_IFAGC R250 1K R251 10K IF_AGC R135 4K7 R134 4K7 R249 1K...

Page 69: ...V AUDIO OUT R338 120R 1 2 P904 F904 F903 F902 F901 1 2 D904 PESD5V0S1BL NC 2 1 D903 PESD5V0S1BL 2 1 D902 PESD5V0S1BL 2 1 PESD5V0S1BL D901 C916 0 1U C915 220P C914 470P C913 470P C912 150P NC C911 150P...

Page 70: ...36 0 1U C935 0 047U 10U C934 0 1U C933 B C E Q903 BT3904 E C B BT3904 Q902 B C E Q901 BT3904 E C B BT3904 Q900 R970 100K R969 75R R968 910R 47K R967 R966 47K 47K R965 47K R964 100R R963 100R R962 R961...

Page 71: ...reset time is 80ms When input is 12V reset vol 8 4V MTK Reset at low level Bottom SIDE SOC POWER SOC EMMC SOC CI SOC RESET SOC USB SOC Ethernet STRAPPING OPCTRL3 eMMC pins share pins w s NAND ICE moc...

Page 72: ...AG6 AF9 AG9 AF12 AH4 AF11 AG4 AG10 AF5 AH10 AF6 U4 Y15 W15 AB4 AC9 AE3 AE6 AD9 AE4 AC11 AD5 AE9 AE5 AE7 AD11 AE12 AC5 AE10 AE11 AD7 AE8 AC7 V4 W4 AA5 AA6 AC4 W5 W6 U6 AA4 Y4 U5 AE13 W9 W8 Y8 Y9 AC20 A...

Page 73: ...A 9 9 R333 4K7 47R R332 R331 47R R330 47R 47R R329 47R R328 R327 47R R326 47R 47R R325 47R R324 R323 47R W6 W5 K2 H3 H4 H5 J2 J3 J4 J5 J6 T5 H6 U5 U9 T10 N5 M6 AA3 AA5 Y4 W4 K6 K4 M7 P5 R10 U8 Y2 Y5 A...

Page 74: ...TA LRCIN SDA SCL RESET VSS RB VDDRB VDDLB LB GNDL NC2 VDDLA LA VDD SA0 MCLK BCLK 5 5 5 5 RED WHITE 5 5 1 5 7 7 Close to SOC AD82587D_12V 9 9 12V_AMP 22UH L604 22UH L603 L602 22UH 22UH L601 L600 120R 0...

Page 75: ...VDS Panel Power 4 LG_DIM_OUT are PWM port 5 DIM_SW_OUT is from DIM switch circuit 6 IIC option for panel 7 Default value in this diagram is for panel without IIC 8 DIM option for MCU 9 Define MCU port...

Page 76: ...3 4 CN802 FSW C774 100P B801 100P C807 1000P C830 B770 R832 10K NC Q770 A0D256 R785 0 33R EN 25V 470U C832 C851 47U 100V R824 0R FB C806 100P R853B 4 7K ZD851 33V R853A 4 7K ZD850 33V 12VOUT R823 0R...

Page 77: ...IIC bus Check the peripheral circuit of mail IC check solder of main IC check data fo NVM and reset it Check reset signal of main no switch on Check 3 3V 12V 24V of power supply Check PW Check DC DC p...

Page 78: ...IC check LVDS cable Check crystal frequence Check the peripheral circuit of mail IC updating SW reset NVM replace main IC Abnormal picture All signal source bad Individual signal source bad Check the...

Page 79: ...e function Abnormal sound Check all sound source Individual sound signal source Check the sound signal link to main IC Check the peripheral circuit of main IC SW Check the power of sound IC Check soun...

Page 80: ......

Page 81: ...1 3 2 D101 0BAV99 NC 0 1U C112 0 1U C110 R110 220R R109 4K7 R113 22K LED R111 1K 3V3SB F101 ZIR_GND ZIR_IN KEY 1 2 3 4 5 P101 1 2 3 4 P102 CDG6 33P NC CDG7 0 01U RDG5 36K CDJ3 22U CDJ4 22U POWER_ON R...

Page 82: ...U CT7 1K RT7 TU_SCL TU_SDA 33R RT26 NC 10K RT25 3V3 CT55 22P NC CT56 22P NC CT54 22P CT53 22P 6800P CT52 CT51 10U CT50 0 022U 6 11 10 7 8 1 3 2 4 5 9 TUN2 C203 10U 3 2 1 4 5 U202 RT8096A 1 2 3 4 AS111...

Page 83: ...VGA_5V R317 100R C323 0 1U R325 220R R324 120R 1 2 D304 PESD5V0S1BL NC UART_TX VGA_SOG_IN VGA_RXD VGA_TXD C321 33P NC NC 33P C320 C319 10P NC C318 10P NC C317 0 01U C316 0 01U C315 0 01U C313 0 01U C...

Page 84: ...D424 9 10 8 7 6 5 4 3 1 2 ESD 13 ESD5V5 O4B0P5 D423 9 10 8 7 6 5 4 3 1 2 ESD 13 ESD5V5 O4B0P5 D421 H3_SDA 9 10 8 7 6 5 4 3 1 2 ESD 13 ESD5V5 O4B0P5 D422 9 10 8 7 6 5 4 3 1 2 ESD 13 ESD5V5 O4B0P5 D419...

Page 85: ...EMMC SOC CI SOC RESET SOC USB SOC Ethernet STRAPPING OPCTRL3 eMMC pins share pins w s NAND ICE moce 24M ROM to eMMC boot from ICE moce 24M ROM to 60bit ECC Nand boot ICE mode 24M serial boot 0 0 1 1 S...

Page 86: ...1_BA2 RA3 RA13 1_A3 RA7 RWE RODT 1_CAS RRAS 1_RAS 0 1U C636 DDR_1V5 DDR_1V5 DDR_1V5 DDR_1V5 DDR_1V5 DDR_1V5 DDR_1V5 DDR_1V5 DDR_1V5 A_VREFCA1 DDRVREF_A1 0 1U C630 0 1U C629 C625 0 1U 0 1U C624 1U C623...

Page 87: ...20 0 1U R742 10K C716 0 1U 0 1U C714 0 1U C709 C708 0 1U 0 1U C707 C706 0 1U C703 0 1U NC 0 1U C702 R744 10K R741 10K R740 10K R736 47R R735 47R R734 47R R733 47R R732 47R R731 47R R730 47R R729 47R R...

Page 88: ...B VDDRB VDDLB LB GNDL NC2 VDDLA LA VDD SA0 MCLK BCLK GND GND GND 5 5 5 5 RED WHITE 5 5 1 5 7 7 Close to SOC AD82587D_12V 9 9 C827 0 1U C826 0 1U C824 0 1U C825 0 1U 1 2 P802 1 2 P801 C802 1000P C801 0...

Page 89: ...on for MCU 9 Define MCU port 3D_FORMAT0 as TCON_WP_OUT for panel AUO T500HVN04 5 3 Place P901 close to P902 on the same PCB board R910 R911 R913 R914 R915 R916 5 Place it as close to SOC as possible 5...

Page 90: ...A A K K D113 R126 R128 C120 C118 C129 PFC VCC C130 C119 C121 C128 C127 R127 R133 FB 1 CMP 2 RT 3 RTZC 4 IS 5 GND 6 OUT 7 VCC 8 U101 R131 C122 LF103 PWON 12VA 48V 12V IS1 IS1 FB FB 4 CS 5 STB 6 MODE 7...

Page 91: ...ISW 6 ENA 5 ISET 2 ISEN4 1 VIN 9 LPF 10 SSTCM P 11 PWM 12 ISEN1 13 ISEN2 14 GND 15 ISEN3 16 U201 C205 R224 R222 R213 C211 R241 C219 VREFB R234 C210 R239 ENA ISEN4 ISEN3 VREFB OVP 3 VREF 8 RT 4 LDR 7...

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