Tatung T3274, User Manual

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3-8 Chapter 3: BIOS Setup
Options and description of each item as follows:
Item Options Description
SDRAM RAS To
CAS Delay
Specifies the length of the delay
inserted between the RAS and
CAS signals of the DRAM
system memory access cycle.
SDRAM RAS
Precharge
Timing
3 Clks
2 Clks
Specifies the length of the RAS
precharge part of the DRAM
system memory access cycle.
DRAM Integrity
Mode
Non-ECC
EC Only
ECC Sets the type of system memory
checking:
Non-ECC - No error checking or
reporting done.
EC only - Multi-bit errors are
detected and reported as parity
errors. Single-bit errors are
corrected by the chipset.
Corrected bits are not written
back to DRAM.
ECC - Multi-bit errors are
detected and reported as parity
errors. Single-bit errors are
corrected by the chipset and
written back to DRAM.