TASKING iSYSTEM Cypress CYT2B7, Hardware User Manual, Page: 14 / 24

winIDEA configuration
By default, P18 port pins (P18_3 – P18_7) or P22 port pins (P22_0 – P22_4) are set as GPIO
pins. To configure these pins as trace pins in winIDEA, open Hardware
menu / CPU Options /
Analyzer tab and add a script
CYT2Bx_TraceInit.cpp
in the SoC Initialization section. Via the
Parameters options and depending on the user target board configuration allocate:
·
TRACE CLOCK Port to PORT 18 (or PORT 22),
·
TRACE DATAn PORT to PORT 18 (or PORT 22).
More information in winIDEA Help .